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SpencerAbsonSpencerAbson
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[AArch64] Add assembly/disassembly for zeroing SVE REV{B,H,W,D} and RBIT (#114110)
This patch adds assembly/disassembly for the following SVE2.2 instructions - RBIT (zeroing) - REVB (zeroing) - REVH (zeroing) - REVW (zeroing) - REVD (zeroing) - In accordance with: https://developer.arm.com/documentation/ddi0602/2024-09/SVE-Instructions Co-authored-by: Marian Lukac [email protected]
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‎llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td‎

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -4322,6 +4322,13 @@ let Predicates = [HasSVE2p2orSME2p2] in {
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// SVE predicate count
43234323
defm FIRSTP_XPP : sve_int_pcount_pred_tmp<0b001, "firstp">;
43244324
defm LASTP_XPP : sve_int_pcount_pred_tmp<0b010, "lastp">;
4325+
4326+
// SVE reverse within elements, zeroing predicate
4327+
defm RBIT_ZPzZ : sve_int_perm_rev_rbit_z<"rbit">;
4328+
defm REVB_ZPzZ : sve_int_perm_rev_revb_z<"revb">;
4329+
defm REVH_ZPzZ : sve_int_perm_rev_revh_z<"revh">;
4330+
def REVW_ZPzZ : sve_int_perm_rev_z<0b11, 0b0110, "revw", ZPR64>;
4331+
def REVD_ZPzZ : sve_int_perm_rev_z<0b00, 0b1110, "revd", ZPR128>;
43254332
} // End HasSME2p2orSVE2p2
43264333

43274334
//===----------------------------------------------------------------------===//

‎llvm/lib/Target/AArch64/SVEInstrFormats.td‎

Lines changed: 39 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -7429,6 +7429,45 @@ multiclass sve_int_perm_rev_revw<string asm, SDPatternOperator op> {
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def : SVE_1_Op_Passthru_Pat<nxv2i64, op, nxv2i1, nxv2i64, !cast<Instruction>(NAME # _D)>;
74307430
}
74317431

7432+
class sve_int_perm_rev_z<bits<2> sz, bits<4> opc, string asm,
7433+
ZPRRegOp zprty>
7434+
: I<(outs zprty:$Zd), (ins PPR3bAny:$Pg, zprty:$Zn),
7435+
asm, "\t$Zd, $Pg/z, $Zn",
7436+
"",
7437+
[]>, Sched<[]> {
7438+
bits<5> Zd;
7439+
bits<3> Pg;
7440+
bits<5> Zn;
7441+
let Inst{31-24} = 0b00000101;
7442+
let Inst{23-22} = sz;
7443+
let Inst{21-20} = 0b10;
7444+
let Inst{19-16} = opc;
7445+
let Inst{15-13} = 0b101;
7446+
let Inst{12-10} = Pg;
7447+
let Inst{9-5} = Zn;
7448+
let Inst{4-0} = Zd;
7449+
7450+
let hasSideEffects = 0;
7451+
}
7452+
7453+
multiclass sve_int_perm_rev_rbit_z<string asm> {
7454+
def _B : sve_int_perm_rev_z<0b00, 0b0111, asm, ZPR8>;
7455+
def _H : sve_int_perm_rev_z<0b01, 0b0111, asm, ZPR16>;
7456+
def _S : sve_int_perm_rev_z<0b10, 0b0111, asm, ZPR32>;
7457+
def _D : sve_int_perm_rev_z<0b11, 0b0111, asm, ZPR64>;
7458+
}
7459+
7460+
multiclass sve_int_perm_rev_revb_z<string asm> {
7461+
def _H : sve_int_perm_rev_z<0b01, 0b0100, asm, ZPR16>;
7462+
def _S : sve_int_perm_rev_z<0b10, 0b0100, asm, ZPR32>;
7463+
def _D : sve_int_perm_rev_z<0b11, 0b0100, asm, ZPR64>;
7464+
}
7465+
7466+
multiclass sve_int_perm_rev_revh_z<string asm> {
7467+
def _S : sve_int_perm_rev_z<0b10, 0b0101, asm, ZPR32>;
7468+
def _D : sve_int_perm_rev_z<0b11, 0b0101, asm, ZPR64>;
7469+
}
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class sve_int_perm_cpy_r<bits<2> sz8_64, string asm, ZPRRegOp zprty,
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RegisterClass srcRegType>
74347473
: I<(outs zprty:$Zd), (ins zprty:$_Zd, PPR3bAny:$Pg, srcRegType:$Rn),

‎llvm/test/MC/AArch64/SME/revd-diagnostics.s‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -11,7 +11,7 @@ revd z0.q, p8/m, z0.q
1111

1212
// wrong predication qualifier, expected /m.
1313
revd z0.q, p0/z, z0.q
14-
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
14+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction requires: sme2p2 or sve2p2
1515
// CHECK-NEXT: revd z0.q, p0/z, z0.q
1616
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
1717

‎llvm/test/MC/AArch64/SVE2p2/rbit_z-diagnostics.s‎

Lines changed: 74 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,74 @@
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/ RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 2>&1 < %s| FileCheck %s
2+
3+
// ------------------------------------------------------------------------- //
4+
// Invalid predicate
5+
6+
rbit z0.b, p8/z, z0.b
7+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
8+
// CHECK-NEXT: rbit z0.b, p8/z, z0.b
9+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
10+
11+
rbit z0.h, p8/z, z0.h
12+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
13+
// CHECK-NEXT: rbit z0.h, p8/z, z0.h
14+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
15+
16+
rbit z0.s, p8/z, z0.s
17+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
18+
// CHECK-NEXT: rbit z0.s, p8/z, z0.s
19+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
20+
21+
rbit z0.d, p8/z, z0.d
22+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
23+
// CHECK-NEXT: rbit z0.d, p8/z, z0.d
24+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
25+
26+
// --------------------------------------------------------------------------//
27+
// Invalid element widths
28+
29+
rbit z0.b, p7/z, z0.d
30+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
31+
// CHECK-NEXT: rbit z0.b, p7/z, z0.d
32+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
33+
34+
rbit z0.h, p7/z, z0.b
35+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
36+
// CHECK-NEXT: rbit z0.h, p7/z, z0.b
37+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
38+
39+
rbit z0.s, p7/z, z0.h
40+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
41+
// CHECK-NEXT: rbit z0.s, p7/z, z0.h
42+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
43+
44+
rbit z0.d, p7/z, z0.s
45+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
46+
// CHECK-NEXT: rbit z0.d, p7/z, z0.s
47+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
48+
49+
// --------------------------------------------------------------------------//
50+
// Negative tests for instructions that are incompatible with movprfx
51+
52+
movprfx z0.b, p0/z, z7.b
53+
rbit z0.b, p0/z, z0.b
54+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
55+
// CHECK-NEXT: rbit z0.b, p0/z, z0.b
56+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
57+
58+
movprfx z0, z7
59+
rbit z0.h, p0/z, z0.h
60+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
61+
// CHECK-NEXT: rbit z0.h, p0/z, z0.h
62+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
63+
64+
movprfx z0.s, p0/z, z7.s
65+
rbit z0.s, p0/z, z0.s
66+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
67+
// CHECK-NEXT: rbit z0.s, p0/z, z0.s
68+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
69+
70+
movprfx z0, z7
71+
rbit z0.d, p0/z, z0.d
72+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
73+
// CHECK-NEXT: rbit z0.d, p0/z, z0.d
74+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

‎llvm/test/MC/AArch64/SVE2p2/rbit_z.s‎

Lines changed: 45 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,45 @@
1+
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 < %s \
2+
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
3+
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2 < %s \
4+
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
5+
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
6+
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
7+
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p2 < %s \
8+
// RUN: | llvm-objdump -d --mattr=+sve2p2 - | FileCheck %s --check-prefix=CHECK-INST
9+
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p2 < %s \
10+
// RUN: | llvm-objdump -d --mattr=-sve - | FileCheck %s --check-prefix=CHECK-UNKNOWN
11+
// Disassemble encoding and check the re-encoding (-show-encoding) matches.
12+
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 < %s \
13+
// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
14+
// RUN: | llvm-mc -triple=aarch64 -mattr=+sve2p2 -disassemble -show-encoding \
15+
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
16+
17+
rbit z0.b, p0/z, z0.b // 00000101-00100111-10100000-00000000
18+
// CHECK-INST: rbit z0.b, p0/z, z0.b
19+
// CHECK-ENCODING: [0x00,0xa0,0x27,0x05]
20+
// CHECK-ERROR: instruction requires: sme2p2 or sve2p2
21+
// CHECK-UNKNOWN: 0527a000 <unknown>
22+
23+
rbit z21.b, p5/z, z10.b // 00000101-00100111-10110101-01010101
24+
// CHECK-INST: rbit z21.b, p5/z, z10.b
25+
// CHECK-ENCODING: [0x55,0xb5,0x27,0x05]
26+
// CHECK-ERROR: instruction requires: sme2p2 or sve2p2
27+
// CHECK-UNKNOWN: 0527b555 <unknown>
28+
29+
rbit z23.h, p3/z, z13.h // 00000101-01100111-10101101-10110111
30+
// CHECK-INST: rbit z23.h, p3/z, z13.h
31+
// CHECK-ENCODING: [0xb7,0xad,0x67,0x05]
32+
// CHECK-ERROR: instruction requires: sme2p2 or sve2p2
33+
// CHECK-UNKNOWN: 0567adb7 <unknown>
34+
35+
rbit z23.s, p3/z, z13.s // 00000101-10100111-10101101-10110111
36+
// CHECK-INST: rbit z23.s, p3/z, z13.s
37+
// CHECK-ENCODING: [0xb7,0xad,0xa7,0x05]
38+
// CHECK-ERROR: instruction requires: sme2p2 or sve2p2
39+
// CHECK-UNKNOWN: 05a7adb7 <unknown>
40+
41+
rbit z31.d, p7/z, z31.d // 00000101-11100111-10111111-11111111
42+
// CHECK-INST: rbit z31.d, p7/z, z31.d
43+
// CHECK-ENCODING: [0xff,0xbf,0xe7,0x05]
44+
// CHECK-ERROR: instruction requires: sme2p2 or sve2p2
45+
// CHECK-UNKNOWN: 05e7bfff <unknown>

‎llvm/test/MC/AArch64/SVE2p2/revb_z-diagnostics.s‎

Lines changed: 63 additions & 0 deletions
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@@ -0,0 +1,63 @@
1+
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 2>&1 < %s| FileCheck %s
2+
3+
// ------------------------------------------------------------------------- //
4+
// Invalid predicate
5+
6+
revb z0.h, p8/z, z0.h
7+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
8+
// CHECK-NEXT: revb z0.h, p8/z, z0.h
9+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
10+
11+
revb z0.s, p8/z, z0.s
12+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
13+
// CHECK-NEXT: revb z0.s, p8/z, z0.s
14+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
15+
16+
revb z0.d, p8/z, z0.d
17+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
18+
// CHECK-NEXT: revb z0.d, p8/z, z0.d
19+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
20+
21+
// --------------------------------------------------------------------------//
22+
// Invalid element widths
23+
24+
revb z0.b, p7/z, z0.b
25+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
26+
// CHECK-NEXT: revb z0.b, p7/z, z0.b
27+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
28+
29+
revb z0.h, p7/z, z0.b
30+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
31+
// CHECK-NEXT: revb z0.h, p7/z, z0.b
32+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
33+
34+
revb z0.s, p7/z, z0.h
35+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
36+
// CHECK-NEXT: revb z0.s, p7/z, z0.h
37+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
38+
39+
revb z0.d, p7/z, z0.s
40+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
41+
// CHECK-NEXT: revb z0.d, p7/z, z0.s
42+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
43+
44+
// --------------------------------------------------------------------------//
45+
// Negative tests for instructions that are incompatible with movprfx
46+
47+
movprfx z0, z7
48+
revb z0.h, p0/z, z0.h
49+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
50+
// CHECK-NEXT: revb z0.h, p0/z, z0.h
51+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
52+
53+
movprfx z0.s, p0/z, z7.s
54+
revb z0.s, p0/z, z0.s
55+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
56+
// CHECK-NEXT: revb z0.s, p0/z, z0.s
57+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
58+
59+
movprfx z0, z7
60+
revb z0.d, p0/z, z0.d
61+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
62+
// CHECK-NEXT: revb z0.d, p0/z, z0.d
63+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

‎llvm/test/MC/AArch64/SVE2p2/revb_z.s‎

Lines changed: 33 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,33 @@
1+
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 < %s \
2+
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
3+
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2 < %s \
4+
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
5+
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
6+
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
7+
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p2 < %s \
8+
// RUN: | llvm-objdump -d --mattr=+sve2p2 - | FileCheck %s --check-prefix=CHECK-INST
9+
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p2 < %s \
10+
// RUN: | llvm-objdump -d --mattr=-sve - | FileCheck %s --check-prefix=CHECK-UNKNOWN
11+
// Disassemble encoding and check the re-encoding (-show-encoding) matches.
12+
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 < %s \
13+
// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
14+
// RUN: | llvm-mc -triple=aarch64 -mattr=+sve2p2 -disassemble -show-encoding \
15+
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
16+
17+
revb z0.h, p0/z, z0.h // 00000101-01100100-10100000-00000000
18+
// CHECK-INST: revb z0.h, p0/z, z0.h
19+
// CHECK-ENCODING: [0x00,0xa0,0x64,0x05]
20+
// CHECK-ERROR: instruction requires: sme2p2 or sve2p2
21+
// CHECK-UNKNOWN: 0564a000 <unknown>
22+
23+
revb z23.s, p3/z, z13.s // 00000101-10100100-10101101-10110111
24+
// CHECK-INST: revb z23.s, p3/z, z13.s
25+
// CHECK-ENCODING: [0xb7,0xad,0xa4,0x05]
26+
// CHECK-ERROR: instruction requires: sme2p2 or sve2p2
27+
// CHECK-UNKNOWN: 05a4adb7 <unknown>
28+
29+
revb z31.d, p7/z, z31.d // 00000101-11100100-10111111-11111111
30+
// CHECK-INST: revb z31.d, p7/z, z31.d
31+
// CHECK-ENCODING: [0xff,0xbf,0xe4,0x05]
32+
// CHECK-ERROR: instruction requires: sme2p2 or sve2p2
33+
// CHECK-UNKNOWN: 05e4bfff <unknown>

‎llvm/test/MC/AArch64/SVE2p2/revd_z-diagnostics.s‎

Lines changed: 56 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,56 @@
1+
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 2>&1 < %s| FileCheck %s
2+
3+
// ------------------------------------------------------------------------- //
4+
// Invalid predicate
5+
6+
revd z0.q, p8/z, z0.q
7+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
8+
// CHECK-NEXT: revd z0.q, p8/z, z0.q
9+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
10+
11+
// --------------------------------------------------------------------------//
12+
// Invalid element widths
13+
14+
revd z0.b, p7/z, z0.b
15+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
16+
// CHECK-NEXT: revd z0.b, p7/z, z0.b
17+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
18+
19+
revd z0.h, p7/z, z0.h
20+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
21+
// CHECK-NEXT: revd z0.h, p7/z, z0.h
22+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
23+
24+
revd z0.s, p7/z, z0.s
25+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
26+
// CHECK-NEXT: revd z0.s, p7/z, z0.s
27+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
28+
29+
revd z0.h, p7/z, z0.b
30+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
31+
// CHECK-NEXT: revd z0.h, p7/z, z0.b
32+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
33+
34+
revd z0.s, p7/z, z0.h
35+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
36+
// CHECK-NEXT: revd z0.s, p7/z, z0.h
37+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
38+
39+
revd z0.d, p7/z, z0.s
40+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
41+
// CHECK-NEXT: revd z0.d, p7/z, z0.s
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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revd z0.q, p7/z, z0.d
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: revd z0.q, p7/z, z0.d
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Negative tests for instructions that are incompatible with movprfx
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movprfx z0, z7
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revd z0.q, p0/z, z0.q
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
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// CHECK-NEXT: revd z0.q, p0/z, z0.q
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

‎llvm/test/MC/AArch64/SVE2p2/revd_z.s‎

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// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 < %s \
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// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
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// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2 < %s \
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// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
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// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
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// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
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// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p2 < %s \
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// RUN: | llvm-objdump -d --mattr=+sve2p2 - | FileCheck %s --check-prefix=CHECK-INST
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// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p2 < %s \
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// RUN: | llvm-objdump -d --mattr=-sve - | FileCheck %s --check-prefix=CHECK-UNKNOWN
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// Disassemble encoding and check the re-encoding (-show-encoding) matches.
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// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 < %s \
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// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
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// RUN: | llvm-mc -triple=aarch64 -mattr=+sve2p2 -disassemble -show-encoding \
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// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
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revd z0.q, p0/z, z0.q // 00000101-00101110-10100000-00000000
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// CHECK-INST: revd z0.q, p0/z, z0.q
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// CHECK-ENCODING: [0x00,0xa0,0x2e,0x05]
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// CHECK-ERROR: instruction requires: sme2p2 or sve2p2
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// CHECK-UNKNOWN: 052ea000 <unknown>
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revd z23.q, p3/z, z13.q // 00000101-00101110-10101101-10110111
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// CHECK-INST: revd z23.q, p3/z, z13.q
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// CHECK-ENCODING: [0xb7,0xad,0x2e,0x05]
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// CHECK-ERROR: instruction requires: sme2p2 or sve2p2
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// CHECK-UNKNOWN: 052eadb7 <unknown>
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revd z31.q, p7/z, z31.q // 00000101-00101110-10111111-11111111
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// CHECK-INST: revd z31.q, p7/z, z31.q
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// CHECK-ENCODING: [0xff,0xbf,0x2e,0x05]
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// CHECK-ERROR: instruction requires: sme2p2 or sve2p2
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// CHECK-UNKNOWN: 052ebfff <unknown>

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