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1 parent 7108dec commit c51417dCopy full SHA for c51417d
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -3308,7 +3308,7 @@ static bool analyzeCandidate(outliner::Candidate &C) {
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// Filter out candidates where the X5 register (t0) can't be used to setup
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// the function call.
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const TargetRegisterInfo *TRI = C.getMF()->getSubtarget().getRegisterInfo();
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- if (std::any_of(C.begin(), C.end(), [TRI](const MachineInstr &MI) {
+ if (llvm::any_of(C, [TRI](const MachineInstr &MI) {
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return isMIModifiesReg(MI, TRI, RISCV::X5);
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}))
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return true;
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