[MIPS] Add Scheduling model for MIPS i6400 and i6500 CPUs

Add scheduling model for the MIPS i6400 and i6500, an in-order
MIPS64R6 processor.

i6400 and i6500 share same instruction latencies.

CPU has following pipelines
  - Two ALUs
  - Multiply and Divide unit (MDU)
  - Branch Unit (CTU)
  - Load/Store Unit (LSU)
  - Short Floating-point Unit and
  - Long Floating-point Unit

Author: mgoudar

llvm/lib/Target/Mips/Mips.td

@@ -224,6 +224,7 @@ include "MipsRegisterBanks.td"
 include "MipsCombine.td"
 
 // Avoid forward declaration issues.
+include "MipsScheduleI6400.td"
 include "MipsScheduleP5600.td"
 include "MipsScheduleGeneric.td"
 
@@ -271,8 +272,8 @@ def : Proc<"mips64r6", [FeatureMips64r6]>;
 def : Proc<"octeon", [FeatureMips64r2, FeatureCnMips]>;
 def : Proc<"octeon+", [FeatureMips64r2, FeatureCnMips, FeatureCnMipsP]>;
 def : ProcessorModel<"p5600", MipsP5600Model, [ImplP5600]>;
-def : ProcessorModel<"i6400", NoSchedModel, [ImplI6400]>;
-def : ProcessorModel<"i6500", NoSchedModel, [ImplI6500]>;
+def : ProcessorModel<"i6400", MipsI6400Model, [ImplI6400]>;
+def : ProcessorModel<"i6500", MipsI6400Model, [ImplI6500]>;
 
 def MipsAsmParser : AsmParser {
   let ShouldEmitMatchRegisterName = 0;

llvm/lib/Target/Mips/Mips32r6InstrInfo.td

@@ -983,7 +983,10 @@ let AdditionalPredicates = [NotInMicroMips] in {
   def SEL_S : R6MMR6Rel, SEL_S_ENC, SEL_S_DESC, ISA_MIPS32R6, HARDFLOAT;
   def SDC2_R6 : SDC2_R6_ENC, SDC2_R6_DESC, ISA_MIPS32R6;
   def SWC2_R6 : SWC2_R6_ENC, SWC2_R6_DESC, ISA_MIPS32R6;
-  def SIGRIE : SIGRIE_ENC, SIGRIE_DESC, ISA_MIPS32R6;
+  
+  let hasNoSchedulingInfo = 1 in {
+    def SIGRIE : SIGRIE_ENC, SIGRIE_DESC, ISA_MIPS32R6;
+  }
 }
 
 let AdditionalPredicates = [NotInMicroMips] in {
@@ -996,8 +999,10 @@ let AdditionalPredicates = [NotInMicroMips] in {
 }
 
 let AdditionalPredicates = [NotInMicroMips] in {
-  def GINVI : R6MMR6Rel, GINVI_ENC, GINVI_DESC, ISA_MIPS32R6, ASE_GINV;
-  def GINVT : R6MMR6Rel, GINVT_ENC, GINVT_DESC, ISA_MIPS32R6, ASE_GINV;
+  let hasNoSchedulingInfo = 1 in {
+    def GINVI : R6MMR6Rel, GINVI_ENC, GINVI_DESC, ISA_MIPS32R6, ASE_GINV;
+    def GINVT : R6MMR6Rel, GINVT_ENC, GINVT_DESC, ISA_MIPS32R6, ASE_GINV;
+  }
 }
 
 //===----------------------------------------------------------------------===//