@@ -59683,16 +59683,6 @@ static SDValue narrowExtractedVectorSelect(SDNode *Ext, const SDLoc &DL,
5968359683static SDValue combineEXTRACT_SUBVECTOR(SDNode *N, SelectionDAG &DAG,
5968459684 TargetLowering::DAGCombinerInfo &DCI,
5968559685 const X86Subtarget &Subtarget) {
59686- // For AVX1 only, if we are extracting from a 256-bit and+not (which will
59687- // eventually get combined/lowered into ANDNP) with a concatenated operand,
59688- // split the 'and' into 128-bit ops to avoid the concatenate and extract.
59689- // We let generic combining take over from there to simplify the
59690- // insert/extract and 'not'.
59691- // This pattern emerges during AVX1 legalization. We handle it before lowering
59692- // to avoid complications like splitting constant vector loads.
59693-
59694- // Capture the original wide type in the likely case that we need to bitcast
59695- // back to this type.
5969659686 if (!N->getValueType(0).isSimple())
5969759687 return SDValue();
5969859688
@@ -59708,8 +59698,14 @@ static SDValue combineEXTRACT_SUBVECTOR(SDNode *N, SelectionDAG &DAG,
5970859698 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5970959699 SDLoc DL(N);
5971059700
59711- if (Subtarget.hasAVX() && !Subtarget.hasAVX2() &&
59712- TLI.isTypeLegal(InVecVT) &&
59701+ // For AVX1 only, if we are extracting from a 256-bit and+not (which will
59702+ // eventually get combined/lowered into ANDNP) with a concatenated operand,
59703+ // split the 'and' into 128-bit ops to avoid the concatenate and extract.
59704+ // We let generic combining take over from there to simplify the
59705+ // insert/extract and 'not'.
59706+ // This pattern emerges during AVX1 legalization. We handle it before lowering
59707+ // to avoid complications like splitting constant vector loads.
59708+ if (Subtarget.hasAVX() && !Subtarget.hasAVX2() && TLI.isTypeLegal(InVecVT) &&
5971359709 InSizeInBits == 256 && InVecBC.getOpcode() == ISD::AND) {
5971459710 auto isConcatenatedNot = [](SDValue V) {
5971559711 V = peekThroughBitcasts(V);
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