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[VPlan] Use nuw when computing {VF,VScale}xUF (#170710)
These quantities should never unsigned-wrap. This matches the behavior if only VFxUF is used (and not VF): when computing both VF and VFxUF, nuw should hold for each step separately.
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10 files changed

+35
-33
lines changed

10 files changed

+35
-33
lines changed

‎llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp‎

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -4593,7 +4593,8 @@ void VPlanTransforms::materializeVFAndVFxUF(VPlan &Plan, VPBasicBlock *VectorPH,
45934593
VF.replaceAllUsesWith(RuntimeVF);
45944594

45954595
VPValue *UF = Plan.getConstantInt(TCTy, Plan.getUF());
4596-
VPValue *MulByUF = Builder.createNaryOp(Instruction::Mul, {RuntimeVF, UF});
4596+
VPValue *MulByUF = Builder.createOverflowingOp(
4597+
Instruction::Mul, {RuntimeVF, UF}, {true, false});
45974598
VFxUF.replaceAllUsesWith(MulByUF);
45984599
}
45994600

@@ -4881,7 +4882,8 @@ void VPlanTransforms::narrowInterleaveGroups(VPlan &Plan, ElementCount VF,
48814882
if (VF.isScalable()) {
48824883
VPValue *VScale = PHBuilder.createElementCount(
48834884
VectorLoop->getCanonicalIVType(), ElementCount::getScalable(1));
4884-
VPValue *VScaleUF = PHBuilder.createNaryOp(Instruction::Mul, {VScale, UF});
4885+
VPValue *VScaleUF = PHBuilder.createOverflowingOp(
4886+
Instruction::Mul, {VScale, UF}, {true, false});
48854887
Inc->setOperand(1, VScaleUF);
48864888
Plan.getVF().replaceAllUsesWith(VScale);
48874889
} else {

‎llvm/test/Transforms/LoopVectorize/AArch64/pr60831-sve-inv-store-crash.ll‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -59,7 +59,7 @@ define void @test_invar_gep(ptr %dst) #0 {
5959
; IC2-NEXT: [[TMP11:%.*]] = mul nuw i64 [[TMP2]], 4
6060
; IC2-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <vscale x 4 x i64> poison, i64 [[TMP11]], i64 0
6161
; IC2-NEXT: [[TMP21:%.*]] = shufflevector <vscale x 4 x i64> [[BROADCAST_SPLATINSERT]], <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer
62-
; IC2-NEXT: [[TMP3:%.*]] = mul i64 [[TMP11]], 2
62+
; IC2-NEXT: [[TMP3:%.*]] = mul nuw i64 [[TMP11]], 2
6363
; IC2-NEXT: [[N_MOD_VF:%.*]] = urem i64 100, [[TMP3]]
6464
; IC2-NEXT: [[N_VEC:%.*]] = sub i64 100, [[N_MOD_VF]]
6565
; IC2-NEXT: [[TMP5:%.*]] = call <vscale x 4 x i64> @llvm.stepvector.nxv4i64()
@@ -172,7 +172,7 @@ define void @test_invar_gep_var_start(i64 %start, ptr %dst) #0 {
172172
; IC2-NEXT: [[TMP4:%.*]] = mul nuw i64 [[TMP3]], 4
173173
; IC2-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <vscale x 4 x i64> poison, i64 [[TMP4]], i64 0
174174
; IC2-NEXT: [[TMP9:%.*]] = shufflevector <vscale x 4 x i64> [[BROADCAST_SPLATINSERT]], <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer
175-
; IC2-NEXT: [[TMP5:%.*]] = mul i64 [[TMP4]], 2
175+
; IC2-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP4]], 2
176176
; IC2-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP0]], [[TMP5]]
177177
; IC2-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP0]], [[N_MOD_VF]]
178178
; IC2-NEXT: [[TMP6:%.*]] = add i64 [[START]], [[N_VEC]]
@@ -294,7 +294,7 @@ define void @test_invar_gep_var_start_step_2(i64 %start, ptr %dst) #0 {
294294
; IC2-NEXT: [[TMP6:%.*]] = mul nuw i64 [[TMP5]], 4
295295
; IC2-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <vscale x 4 x i64> poison, i64 [[TMP6]], i64 0
296296
; IC2-NEXT: [[BROADCAST_SPLAT1:%.*]] = shufflevector <vscale x 4 x i64> [[BROADCAST_SPLATINSERT]], <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer
297-
; IC2-NEXT: [[TMP7:%.*]] = mul i64 [[TMP6]], 2
297+
; IC2-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP6]], 2
298298
; IC2-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP2]], [[TMP7]]
299299
; IC2-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP2]], [[N_MOD_VF]]
300300
; IC2-NEXT: [[TMP10:%.*]] = mul i64 [[N_VEC]], 2

‎llvm/test/Transforms/LoopVectorize/AArch64/sve-inductions-unusual-types.ll‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -15,7 +15,7 @@ define void @induction_i7(ptr %dst) #0 {
1515
; CHECK-NEXT: [[TMP40:%.*]] = mul nuw i64 [[TMP4]], 2
1616
; CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 2 x i64> poison, i64 [[TMP40]], i64 0
1717
; CHECK-NEXT: [[DOTSPLAT_:%.*]] = shufflevector <vscale x 2 x i64> [[DOTSPLATINSERT]], <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
18-
; CHECK-NEXT: [[TMP5:%.*]] = mul i64 [[TMP40]], 2
18+
; CHECK-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP40]], 2
1919
; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 64, [[TMP5]]
2020
; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 64, [[N_MOD_VF]]
2121
; CHECK-NEXT: [[IND_END:%.*]] = trunc i64 [[N_VEC]] to i7
@@ -74,7 +74,7 @@ define void @induction_i3_zext(ptr %dst) #0 {
7474
; CHECK-NEXT: [[TMP40:%.*]] = mul nuw i64 [[TMP4]], 2
7575
; CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 2 x i64> poison, i64 [[TMP40]], i64 0
7676
; CHECK-NEXT: [[DOTSPLAT_:%.*]] = shufflevector <vscale x 2 x i64> [[DOTSPLATINSERT]], <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
77-
; CHECK-NEXT: [[TMP5:%.*]] = mul i64 [[TMP40]], 2
77+
; CHECK-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP40]], 2
7878
; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 64, [[TMP5]]
7979
; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 64, [[N_MOD_VF]]
8080
; CHECK-NEXT: [[IND_END:%.*]] = trunc i64 [[N_VEC]] to i3

‎llvm/test/Transforms/LoopVectorize/AArch64/sve-vector-reverse.ll‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -21,7 +21,7 @@ define void @vector_reverse_f64(i64 %N, ptr noalias %a, ptr noalias %b) #0{
2121
; CHECK: vector.ph:
2222
; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.vscale.i64()
2323
; CHECK-NEXT: [[TMP5:%.*]] = shl nuw i64 [[TMP4]], 3
24-
; CHECK-NEXT: [[TMP6:%.*]] = shl i64 [[TMP4]], 4
24+
; CHECK-NEXT: [[TMP6:%.*]] = shl nuw i64 [[TMP4]], 4
2525
; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N]], [[TMP6]]
2626
; CHECK-NEXT: [[N_VEC:%.*]] = sub nsw i64 [[N]], [[N_MOD_VF]]
2727
; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
@@ -98,7 +98,7 @@ define void @vector_reverse_i64(i64 %N, ptr %a, ptr %b) #0 {
9898
; CHECK: vector.ph:
9999
; CHECK-NEXT: [[TMP7:%.*]] = call i64 @llvm.vscale.i64()
100100
; CHECK-NEXT: [[TMP8:%.*]] = shl nuw i64 [[TMP7]], 3
101-
; CHECK-NEXT: [[TMP9:%.*]] = shl i64 [[TMP7]], 4
101+
; CHECK-NEXT: [[TMP9:%.*]] = shl nuw i64 [[TMP7]], 4
102102
; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N]], [[TMP9]]
103103
; CHECK-NEXT: [[N_VEC:%.*]] = sub nsw i64 [[N]], [[N_MOD_VF]]
104104
; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]

‎llvm/test/Transforms/LoopVectorize/RISCV/riscv-vector-reverse.ll‎

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -106,7 +106,7 @@ define void @vector_reverse_i32(ptr noalias %A, ptr noalias %B) {
106106
; RV64-UF2: [[VECTOR_PH]]:
107107
; RV64-UF2-NEXT: [[TMP4:%.*]] = call i64 @llvm.vscale.i64()
108108
; RV64-UF2-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP4]], 4
109-
; RV64-UF2-NEXT: [[TMP6:%.*]] = mul i64 [[TMP5]], 2
109+
; RV64-UF2-NEXT: [[TMP6:%.*]] = mul nuw i64 [[TMP5]], 2
110110
; RV64-UF2-NEXT: [[N_VEC:%.*]] = urem i64 1023, [[TMP6]]
111111
; RV64-UF2-NEXT: [[TMP7:%.*]] = sub i64 1023, [[N_VEC]]
112112
; RV64-UF2-NEXT: [[TMP33:%.*]] = sub i64 1023, [[TMP7]]
@@ -236,7 +236,7 @@ define void @vector_reverse_i64(ptr nocapture noundef writeonly %A, ptr nocaptur
236236
; RV64-NEXT: [[INDEX_EVL_NEXT]] = add nuw i64 [[TMP36]], [[INDEX]]
237237
; RV64-NEXT: [[AVL_NEXT]] = sub nuw i64 [[AVL]], [[TMP36]]
238238
; RV64-NEXT: [[TMP37:%.*]] = icmp eq i64 [[AVL_NEXT]], 0
239-
; RV64-NEXT: br i1 [[TMP37]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP8:![0-9]+]]
239+
; RV64-NEXT: br i1 [[TMP37]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]]
240240
; RV64: [[MIDDLE_BLOCK]]:
241241
; RV64-NEXT: br label %[[FOR_COND_CLEANUP_LOOPEXIT:.*]]
242242
; RV64: [[SCALAR_PH]]:
@@ -297,7 +297,7 @@ define void @vector_reverse_i64(ptr nocapture noundef writeonly %A, ptr nocaptur
297297
; RV32-NEXT: [[INDEX_EVL_NEXT]] = add nuw i64 [[TMP29]], [[INDEX]]
298298
; RV32-NEXT: [[AVL_NEXT]] = sub nuw i64 [[AVL]], [[TMP29]]
299299
; RV32-NEXT: [[TMP30:%.*]] = icmp eq i64 [[AVL_NEXT]], 0
300-
; RV32-NEXT: br i1 [[TMP30]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP8:![0-9]+]]
300+
; RV32-NEXT: br i1 [[TMP30]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]]
301301
; RV32: [[MIDDLE_BLOCK]]:
302302
; RV32-NEXT: br label %[[FOR_COND_CLEANUP_LOOPEXIT:.*]]
303303
; RV32: [[SCALAR_PH]]:
@@ -340,7 +340,7 @@ define void @vector_reverse_i64(ptr nocapture noundef writeonly %A, ptr nocaptur
340340
; RV64-UF2: [[VECTOR_PH]]:
341341
; RV64-UF2-NEXT: [[TMP17:%.*]] = call i64 @llvm.vscale.i64()
342342
; RV64-UF2-NEXT: [[TMP18:%.*]] = mul nuw i64 [[TMP17]], 4
343-
; RV64-UF2-NEXT: [[TMP19:%.*]] = mul i64 [[TMP18]], 2
343+
; RV64-UF2-NEXT: [[TMP19:%.*]] = mul nuw i64 [[TMP18]], 2
344344
; RV64-UF2-NEXT: [[N_VEC:%.*]] = urem i64 [[TMP0]], [[TMP19]]
345345
; RV64-UF2-NEXT: [[TMP20:%.*]] = sub i64 [[TMP0]], [[N_VEC]]
346346
; RV64-UF2-NEXT: [[TMP48:%.*]] = sub i64 [[TMP0]], [[TMP20]]
@@ -487,7 +487,7 @@ define void @vector_reverse_f32(ptr nocapture noundef writeonly %A, ptr nocaptur
487487
; RV64-NEXT: [[INDEX_EVL_NEXT]] = add nuw i64 [[TMP36]], [[INDEX]]
488488
; RV64-NEXT: [[AVL_NEXT]] = sub nuw i64 [[AVL]], [[TMP36]]
489489
; RV64-NEXT: [[TMP37:%.*]] = icmp eq i64 [[AVL_NEXT]], 0
490-
; RV64-NEXT: br i1 [[TMP37]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP10:![0-9]+]]
490+
; RV64-NEXT: br i1 [[TMP37]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP5:![0-9]+]]
491491
; RV64: [[MIDDLE_BLOCK]]:
492492
; RV64-NEXT: br label %[[FOR_COND_CLEANUP_LOOPEXIT:.*]]
493493
; RV64: [[SCALAR_PH]]:
@@ -548,7 +548,7 @@ define void @vector_reverse_f32(ptr nocapture noundef writeonly %A, ptr nocaptur
548548
; RV32-NEXT: [[INDEX_EVL_NEXT]] = add nuw i64 [[TMP29]], [[INDEX]]
549549
; RV32-NEXT: [[AVL_NEXT]] = sub nuw i64 [[AVL]], [[TMP29]]
550550
; RV32-NEXT: [[TMP30:%.*]] = icmp eq i64 [[AVL_NEXT]], 0
551-
; RV32-NEXT: br i1 [[TMP30]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP10:![0-9]+]]
551+
; RV32-NEXT: br i1 [[TMP30]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP5:![0-9]+]]
552552
; RV32: [[MIDDLE_BLOCK]]:
553553
; RV32-NEXT: br label %[[FOR_COND_CLEANUP_LOOPEXIT:.*]]
554554
; RV32: [[SCALAR_PH]]:
@@ -591,7 +591,7 @@ define void @vector_reverse_f32(ptr nocapture noundef writeonly %A, ptr nocaptur
591591
; RV64-UF2: [[VECTOR_PH]]:
592592
; RV64-UF2-NEXT: [[TMP17:%.*]] = call i64 @llvm.vscale.i64()
593593
; RV64-UF2-NEXT: [[TMP18:%.*]] = mul nuw i64 [[TMP17]], 4
594-
; RV64-UF2-NEXT: [[TMP19:%.*]] = mul i64 [[TMP18]], 2
594+
; RV64-UF2-NEXT: [[TMP19:%.*]] = mul nuw i64 [[TMP18]], 2
595595
; RV64-UF2-NEXT: [[N_VEC:%.*]] = urem i64 [[TMP0]], [[TMP19]]
596596
; RV64-UF2-NEXT: [[TMP20:%.*]] = sub i64 [[TMP0]], [[N_VEC]]
597597
; RV64-UF2-NEXT: [[TMP48:%.*]] = sub i64 [[TMP0]], [[TMP20]]
@@ -714,7 +714,7 @@ define void @vector_reverse_f32_simplify(ptr noalias %A, ptr noalias %B) {
714714
; RV64-NEXT: [[INDEX_EVL_NEXT]] = add nuw i64 [[TMP22]], [[INDEX]]
715715
; RV64-NEXT: [[AVL_NEXT]] = sub nuw i64 [[AVL]], [[TMP22]]
716716
; RV64-NEXT: [[TMP23:%.*]] = icmp eq i64 [[AVL_NEXT]], 0
717-
; RV64-NEXT: br i1 [[TMP23]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP12:![0-9]+]]
717+
; RV64-NEXT: br i1 [[TMP23]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP7:![0-9]+]]
718718
; RV64: [[MIDDLE_BLOCK]]:
719719
; RV64-NEXT: br label %[[EXIT:.*]]
720720
; RV64: [[EXIT]]:
@@ -753,7 +753,7 @@ define void @vector_reverse_f32_simplify(ptr noalias %A, ptr noalias %B) {
753753
; RV32-NEXT: [[INDEX_EVL_NEXT]] = add nuw i64 [[TMP23]], [[INDEX]]
754754
; RV32-NEXT: [[AVL_NEXT]] = sub nuw i64 [[AVL]], [[TMP23]]
755755
; RV32-NEXT: [[TMP21:%.*]] = icmp eq i64 [[AVL_NEXT]], 0
756-
; RV32-NEXT: br i1 [[TMP21]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP12:![0-9]+]]
756+
; RV32-NEXT: br i1 [[TMP21]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP7:![0-9]+]]
757757
; RV32: [[MIDDLE_BLOCK]]:
758758
; RV32-NEXT: br label %[[EXIT:.*]]
759759
; RV32: [[EXIT]]:
@@ -769,7 +769,7 @@ define void @vector_reverse_f32_simplify(ptr noalias %A, ptr noalias %B) {
769769
; RV64-UF2: [[VECTOR_PH]]:
770770
; RV64-UF2-NEXT: [[TMP4:%.*]] = call i64 @llvm.vscale.i64()
771771
; RV64-UF2-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP4]], 4
772-
; RV64-UF2-NEXT: [[TMP6:%.*]] = mul i64 [[TMP5]], 2
772+
; RV64-UF2-NEXT: [[TMP6:%.*]] = mul nuw i64 [[TMP5]], 2
773773
; RV64-UF2-NEXT: [[N_VEC:%.*]] = urem i64 1023, [[TMP6]]
774774
; RV64-UF2-NEXT: [[TMP7:%.*]] = sub i64 1023, [[N_VEC]]
775775
; RV64-UF2-NEXT: [[TMP33:%.*]] = sub i64 1023, [[TMP7]]
@@ -884,7 +884,7 @@ define void @vector_reverse_irregular_type(ptr noalias %A, ptr noalias %B) {
884884
; RV64-NEXT: store i7 [[TMP28]], ptr [[TMP24]], align 1
885885
; RV64-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
886886
; RV64-NEXT: [[TMP29:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1020
887-
; RV64-NEXT: br i1 [[TMP29]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP13:![0-9]+]]
887+
; RV64-NEXT: br i1 [[TMP29]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP8:![0-9]+]]
888888
; RV64: [[MIDDLE_BLOCK]]:
889889
; RV64-NEXT: br label %[[SCALAR_PH:.*]]
890890
; RV64: [[SCALAR_PH]]:
@@ -935,7 +935,7 @@ define void @vector_reverse_irregular_type(ptr noalias %A, ptr noalias %B) {
935935
; RV32-NEXT: store i7 [[TMP28]], ptr [[TMP24]], align 1
936936
; RV32-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
937937
; RV32-NEXT: [[TMP29:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1020
938-
; RV32-NEXT: br i1 [[TMP29]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP13:![0-9]+]]
938+
; RV32-NEXT: br i1 [[TMP29]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP8:![0-9]+]]
939939
; RV32: [[MIDDLE_BLOCK]]:
940940
; RV32-NEXT: br label %[[SCALAR_PH:.*]]
941941
; RV32: [[SCALAR_PH]]:

‎llvm/test/Transforms/LoopVectorize/RISCV/strided-accesses.ll‎

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -46,7 +46,7 @@ define void @single_constant_stride_int_scaled(ptr %p) {
4646
; CHECK-UF2-NEXT: [[TMP3:%.*]] = mul nuw i64 [[TMP2]], 4
4747
; CHECK-UF2-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <vscale x 4 x i64> poison, i64 [[TMP3]], i64 0
4848
; CHECK-UF2-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <vscale x 4 x i64> [[BROADCAST_SPLATINSERT]], <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer
49-
; CHECK-UF2-NEXT: [[TMP4:%.*]] = mul i64 [[TMP3]], 2
49+
; CHECK-UF2-NEXT: [[TMP4:%.*]] = mul nuw i64 [[TMP3]], 2
5050
; CHECK-UF2-NEXT: [[N_MOD_VF:%.*]] = urem i64 1024, [[TMP4]]
5151
; CHECK-UF2-NEXT: [[TMP5:%.*]] = icmp eq i64 [[N_MOD_VF]], 0
5252
; CHECK-UF2-NEXT: [[TMP6:%.*]] = select i1 [[TMP5]], i64 [[TMP4]], i64 [[N_MOD_VF]]
@@ -150,7 +150,7 @@ define void @single_constant_stride_int_iv(ptr %p) {
150150
; CHECK-UF2-NEXT: [[TMP3:%.*]] = mul nuw i64 [[TMP2]], 4
151151
; CHECK-UF2-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <vscale x 4 x i64> poison, i64 [[TMP3]], i64 0
152152
; CHECK-UF2-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <vscale x 4 x i64> [[BROADCAST_SPLATINSERT]], <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer
153-
; CHECK-UF2-NEXT: [[TMP4:%.*]] = mul i64 [[TMP3]], 2
153+
; CHECK-UF2-NEXT: [[TMP4:%.*]] = mul nuw i64 [[TMP3]], 2
154154
; CHECK-UF2-NEXT: [[N_MOD_VF:%.*]] = urem i64 1024, [[TMP4]]
155155
; CHECK-UF2-NEXT: [[N_VEC:%.*]] = sub i64 1024, [[N_MOD_VF]]
156156
; CHECK-UF2-NEXT: [[TMP5:%.*]] = mul i64 [[N_VEC]], 64
@@ -254,7 +254,7 @@ define void @single_constant_stride_ptr_iv(ptr %p) {
254254
; CHECK-UF2-NEXT: [[TMP3:%.*]] = mul nuw i64 [[TMP2]], 4
255255
; CHECK-UF2-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <vscale x 4 x i64> poison, i64 [[TMP3]], i64 0
256256
; CHECK-UF2-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <vscale x 4 x i64> [[BROADCAST_SPLATINSERT]], <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer
257-
; CHECK-UF2-NEXT: [[TMP4:%.*]] = mul i64 [[TMP3]], 2
257+
; CHECK-UF2-NEXT: [[TMP4:%.*]] = mul nuw i64 [[TMP3]], 2
258258
; CHECK-UF2-NEXT: [[N_MOD_VF:%.*]] = urem i64 1024, [[TMP4]]
259259
; CHECK-UF2-NEXT: [[TMP5:%.*]] = icmp eq i64 [[N_MOD_VF]], 0
260260
; CHECK-UF2-NEXT: [[TMP6:%.*]] = select i1 [[TMP5]], i64 [[TMP4]], i64 [[N_MOD_VF]]
@@ -876,7 +876,7 @@ define void @double_stride_int_scaled(ptr %p, ptr %p2, i64 %stride) {
876876
; STRIDED-UF2-NEXT: [[TMP29:%.*]] = mul nuw i64 [[TMP28]], 4
877877
; STRIDED-UF2-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <vscale x 4 x i64> poison, i64 [[TMP29]], i64 0
878878
; STRIDED-UF2-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <vscale x 4 x i64> [[BROADCAST_SPLATINSERT]], <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer
879-
; STRIDED-UF2-NEXT: [[TMP30:%.*]] = mul i64 [[TMP29]], 2
879+
; STRIDED-UF2-NEXT: [[TMP30:%.*]] = mul nuw i64 [[TMP29]], 2
880880
; STRIDED-UF2-NEXT: [[N_MOD_VF:%.*]] = urem i64 1024, [[TMP30]]
881881
; STRIDED-UF2-NEXT: [[N_VEC:%.*]] = sub i64 1024, [[N_MOD_VF]]
882882
; STRIDED-UF2-NEXT: [[BROADCAST_SPLATINSERT10:%.*]] = insertelement <vscale x 4 x i64> poison, i64 [[STRIDE]], i64 0
@@ -1204,7 +1204,7 @@ define void @double_stride_ptr_iv(ptr %p, ptr %p2, i64 %stride) {
12041204
; STRIDED-UF2-NEXT: [[TMP8:%.*]] = mul nuw i64 [[TMP7]], 4
12051205
; STRIDED-UF2-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <vscale x 4 x i64> poison, i64 [[TMP8]], i64 0
12061206
; STRIDED-UF2-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <vscale x 4 x i64> [[BROADCAST_SPLATINSERT]], <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer
1207-
; STRIDED-UF2-NEXT: [[TMP9:%.*]] = mul i64 [[TMP8]], 2
1207+
; STRIDED-UF2-NEXT: [[TMP9:%.*]] = mul nuw i64 [[TMP8]], 2
12081208
; STRIDED-UF2-NEXT: [[N_MOD_VF:%.*]] = urem i64 1024, [[TMP9]]
12091209
; STRIDED-UF2-NEXT: [[N_VEC:%.*]] = sub i64 1024, [[N_MOD_VF]]
12101210
; STRIDED-UF2-NEXT: [[BROADCAST_SPLATINSERT7:%.*]] = insertelement <vscale x 4 x i64> poison, i64 [[STRIDE]], i64 0
@@ -1335,7 +1335,7 @@ define void @constant_stride_reinterpret(ptr noalias %in, ptr noalias %out) {
13351335
; NOSTRIDED-UF2-NEXT: [[TMP3:%.*]] = mul nuw i64 [[TMP2]], 2
13361336
; NOSTRIDED-UF2-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <vscale x 2 x i64> poison, i64 [[TMP3]], i64 0
13371337
; NOSTRIDED-UF2-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <vscale x 2 x i64> [[BROADCAST_SPLATINSERT]], <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
1338-
; NOSTRIDED-UF2-NEXT: [[TMP4:%.*]] = mul i64 [[TMP3]], 2
1338+
; NOSTRIDED-UF2-NEXT: [[TMP4:%.*]] = mul nuw i64 [[TMP3]], 2
13391339
; NOSTRIDED-UF2-NEXT: [[N_MOD_VF:%.*]] = urem i64 1024, [[TMP4]]
13401340
; NOSTRIDED-UF2-NEXT: [[N_VEC:%.*]] = sub i64 1024, [[N_MOD_VF]]
13411341
; NOSTRIDED-UF2-NEXT: [[TMP5:%.*]] = call <vscale x 2 x i64> @llvm.stepvector.nxv2i64()
@@ -1419,7 +1419,7 @@ define void @constant_stride_reinterpret(ptr noalias %in, ptr noalias %out) {
14191419
; STRIDED-UF2-NEXT: [[TMP3:%.*]] = mul nuw i64 [[TMP2]], 2
14201420
; STRIDED-UF2-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <vscale x 2 x i64> poison, i64 [[TMP3]], i64 0
14211421
; STRIDED-UF2-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <vscale x 2 x i64> [[BROADCAST_SPLATINSERT]], <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
1422-
; STRIDED-UF2-NEXT: [[TMP4:%.*]] = mul i64 [[TMP3]], 2
1422+
; STRIDED-UF2-NEXT: [[TMP4:%.*]] = mul nuw i64 [[TMP3]], 2
14231423
; STRIDED-UF2-NEXT: [[N_MOD_VF:%.*]] = urem i64 1024, [[TMP4]]
14241424
; STRIDED-UF2-NEXT: [[N_VEC:%.*]] = sub i64 1024, [[N_MOD_VF]]
14251425
; STRIDED-UF2-NEXT: [[TMP5:%.*]] = call <vscale x 2 x i64> @llvm.stepvector.nxv2i64()

‎llvm/test/Transforms/LoopVectorize/scalable-assume.ll‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -157,7 +157,7 @@ define void @predicated_assume(ptr noalias nocapture readonly %a, ptr noalias no
157157
; CHECK-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP4]], 2
158158
; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <vscale x 2 x i64> poison, i64 [[TMP5]], i64 0
159159
; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <vscale x 2 x i64> [[BROADCAST_SPLATINSERT]], <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
160-
; CHECK-NEXT: [[TMP6:%.*]] = mul i64 [[TMP5]], 2
160+
; CHECK-NEXT: [[TMP6:%.*]] = mul nuw i64 [[TMP5]], 2
161161
; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N]], [[TMP6]]
162162
; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]]
163163
; CHECK-NEXT: [[TMP7:%.*]] = call <vscale x 2 x i64> @llvm.stepvector.nxv2i64()

‎llvm/test/Transforms/LoopVectorize/scalable-first-order-recurrence.ll‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -673,7 +673,7 @@ define i32 @extract_second_last_iteration(ptr %cval, i32 %x) {
673673
; CHECK-VF4UF2-NEXT: [[TMP5:%.*]] = mul nuw i32 [[TMP4]], 4
674674
; CHECK-VF4UF2-NEXT: [[BROADCAST_SPLATINSERT1:%.*]] = insertelement <vscale x 4 x i32> poison, i32 [[TMP5]], i64 0
675675
; CHECK-VF4UF2-NEXT: [[BROADCAST_SPLAT2:%.*]] = shufflevector <vscale x 4 x i32> [[BROADCAST_SPLATINSERT1]], <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
676-
; CHECK-VF4UF2-NEXT: [[TMP6:%.*]] = mul i32 [[TMP5]], 2
676+
; CHECK-VF4UF2-NEXT: [[TMP6:%.*]] = mul nuw i32 [[TMP5]], 2
677677
; CHECK-VF4UF2-NEXT: [[N_MOD_VF:%.*]] = urem i32 96, [[TMP6]]
678678
; CHECK-VF4UF2-NEXT: [[N_VEC:%.*]] = sub i32 96, [[N_MOD_VF]]
679679
; CHECK-VF4UF2-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <vscale x 4 x i32> poison, i32 [[X]], i64 0

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