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syzaarasyzaara
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[PPC] Add custom lowering for uaddo (#110137)
Improve the codegen for uaddo node for i64 in 64-bit mode and i32 in 32-bit mode by custom lowering.
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5 files changed

+145
-3
lines changed

‎llvm/lib/Target/PowerPC/PPCISelLowering.cpp‎

Lines changed: 42 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -198,6 +198,8 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
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}
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}
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setOperationAction(ISD::UADDO, isPPC64 ? MVT::i64 : MVT::i32, Custom);
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// Match BITREVERSE to customized fast code sequence in the td file.
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setOperationAction(ISD::BITREVERSE, MVT::i32, Legal);
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setOperationAction(ISD::BITREVERSE, MVT::i64, Legal);
@@ -11967,11 +11969,51 @@ SDValue PPCTargetLowering::LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const {
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llvm_unreachable("ERROR:Should return for all cases within swtich.");
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}
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SDValue PPCTargetLowering::LowerUaddo(SDValue Op, SelectionDAG &DAG) const {
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// Default to target independent lowering if there is a logical user of the
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// carry-bit.
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for (SDNode *U : Op->uses()) {
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if (U->getOpcode() == ISD::SELECT)
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return SDValue();
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if (ISD::isBitwiseLogicOp(U->getOpcode())) {
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for (unsigned i = 0, ie = U->getNumOperands(); i != ie; ++i) {
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if (U->getOperand(i).getOpcode() != ISD::UADDO &&
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U->getOperand(i).getOpcode() != ISD::MERGE_VALUES)
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return SDValue();
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}
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}
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}
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SDValue LHS = Op.getOperand(0);
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SDValue RHS = Op.getOperand(1);
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SDLoc dl(Op);
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// Default to target independent lowering for special cases handled there.
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if (isOneConstant(RHS) || isAllOnesConstant(RHS))
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return SDValue();
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EVT VT = Op.getNode()->getValueType(0);
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SDValue ADDC;
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SDValue Overflow;
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SDVTList VTs = Op.getNode()->getVTList();
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ADDC = DAG.getNode(ISD::ADDC, dl, DAG.getVTList(VT, MVT::Glue), LHS, RHS);
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Overflow = DAG.getNode(ISD::ADDE, dl, DAG.getVTList(VT, MVT::Glue),
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DAG.getConstant(0, dl, VT), DAG.getConstant(0, dl, VT),
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ADDC.getValue(1));
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SDValue OverflowTrunc =
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DAG.getNode(ISD::TRUNCATE, dl, Op.getNode()->getValueType(1), Overflow);
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SDValue Res =
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DAG.getNode(ISD::MERGE_VALUES, dl, VTs, ADDC.getValue(0), OverflowTrunc);
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return Res;
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}
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/// LowerOperation - Provide custom lowering hooks for some operations.
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///
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SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
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switch (Op.getOpcode()) {
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default: llvm_unreachable("Wasn't expecting to be able to lower this!");
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case ISD::UADDO: return LowerUaddo(Op, DAG);
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case ISD::FPOW: return lowerPow(Op, DAG);
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case ISD::FSIN: return lowerSin(Op, DAG);
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case ISD::FCOS: return lowerCos(Op, DAG);

‎llvm/lib/Target/PowerPC/PPCISelLowering.h‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1277,6 +1277,7 @@ namespace llvm {
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SDValue LowerGlobalTLSAddressLinux(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerUaddo(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;

‎llvm/test/CodeGen/PowerPC/sat-add.ll‎

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -170,11 +170,10 @@ define i64 @unsigned_sat_constant_i64_using_cmp_sum(i64 %x) {
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define i64 @unsigned_sat_constant_i64_using_cmp_notval(i64 %x) {
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; CHECK-LABEL: unsigned_sat_constant_i64_using_cmp_notval:
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; CHECK: # %bb.0:
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; CHECK-NEXT: li 5, -43
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; CHECK-NEXT: addi 4, 3, 42
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; CHECK-NEXT: cmpld 3, 5
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; CHECK-NEXT: cmpld 4, 3
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; CHECK-NEXT: li 3, -1
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; CHECK-NEXT: iselgt 3, 3, 4
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; CHECK-NEXT: isellt 3, 3, 4
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; CHECK-NEXT: blr
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%a = add i64 %x, 42
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%c = icmp ugt i64 %x, -43

‎llvm/test/CodeGen/PowerPC/uaddo-32.ll‎

Lines changed: 38 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,38 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc < %s -mtriple=powerpc-unknown-linux-gnu | FileCheck %s
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; RUN: llc < %s -mtriple=powerpc-ibm-aix-xcoff | FileCheck %s
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define noundef i32 @add(i32 noundef %a, i32 noundef %b, ptr nocapture noundef writeonly %ovf) {
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; CHECK-LABEL: add:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: li 6, 0
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; CHECK-NEXT: addc 3, 3, 4
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; CHECK-NEXT: addze 4, 6
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; CHECK-NEXT: stw 4, 0(5)
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; CHECK-NEXT: blr
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entry:
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%0 = tail call { i32, i1 } @llvm.uadd.with.overflow.i32(i32 %a, i32 %b)
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%1 = extractvalue { i32, i1 } %0, 1
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%2 = extractvalue { i32, i1 } %0, 0
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%3 = zext i1 %1 to i32
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store i32 %3, ptr %ovf, align 8
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ret i32 %2
20+
}
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declare { i32, i1 } @llvm.uadd.with.overflow.i32(i32, i32)
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define noundef zeroext i1 @add_overflow(i32 noundef %a, i32 noundef %b, ptr nocapture noundef writeonly %ovf) {
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; CHECK-LABEL: add_overflow:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: li 6, 0
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; CHECK-NEXT: addc 4, 3, 4
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; CHECK-NEXT: addze 3, 6
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; CHECK-NEXT: stw 4, 0(5)
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; CHECK-NEXT: blr
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entry:
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%0 = tail call { i32, i1 } @llvm.uadd.with.overflow.i32(i32 %a, i32 %b)
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%1 = extractvalue { i32, i1 } %0, 1
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%2 = extractvalue { i32, i1 } %0, 0
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store i32 %2, ptr %ovf, align 8
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ret i1 %1
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}

‎llvm/test/CodeGen/PowerPC/uaddo-64.ll‎

Lines changed: 62 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,62 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu | FileCheck %s
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; RUN: llc < %s -mtriple=powerpc64-ibm-aix-xcoff | FileCheck %s
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define noundef i64 @add(i64 noundef %a, i64 noundef %b, ptr nocapture noundef writeonly %ovf) {
6+
; CHECK-LABEL: add:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: li 6, 0
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; CHECK-NEXT: addc 3, 3, 4
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; CHECK-NEXT: addze 4, 6
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; CHECK-NEXT: std 4, 0(5)
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; CHECK-NEXT: blr
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entry:
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%0 = tail call { i64, i1 } @llvm.uadd.with.overflow.i64(i64 %a, i64 %b)
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%1 = extractvalue { i64, i1 } %0, 1
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%2 = extractvalue { i64, i1 } %0, 0
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%3 = zext i1 %1 to i64
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store i64 %3, ptr %ovf, align 8
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ret i64 %2
20+
}
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declare { i64, i1 } @llvm.uadd.with.overflow.i64(i64, i64)
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define noundef zeroext i1 @add_overflow(i64 noundef %a, i64 noundef %b, ptr nocapture noundef writeonly %ovf) {
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; CHECK-LABEL: add_overflow:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: li 6, 0
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; CHECK-NEXT: addc 4, 3, 4
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; CHECK-NEXT: addze 3, 6
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; CHECK-NEXT: std 4, 0(5)
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; CHECK-NEXT: blr
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entry:
33+
%0 = tail call { i64, i1 } @llvm.uadd.with.overflow.i64(i64 %a, i64 %b)
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%1 = extractvalue { i64, i1 } %0, 1
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%2 = extractvalue { i64, i1 } %0, 0
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store i64 %2, ptr %ovf, align 8
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ret i1 %1
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}
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define noundef i64 @addWithCarryIn (i64 noundef %a, i64 noundef %b, i64 noundef %c, ptr nocapture noundef writeonly %ovf) {
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; CHECK-LABEL: addWithCarryIn:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: li 7, 0
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; CHECK-NEXT: addc 3, 3, 4
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; CHECK-NEXT: addze 4, 7
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; CHECK-NEXT: addc 3, 3, 5
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; CHECK-NEXT: addze 5, 7
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; CHECK-NEXT: or 4, 4, 5
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; CHECK-NEXT: std 4, 0(6)
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; CHECK-NEXT: blr
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entry:
52+
%0 = tail call { i64, i1 } @llvm.uadd.with.overflow.i64(i64 %a, i64 %b)
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%1 = extractvalue { i64, i1 } %0, 1
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%2 = extractvalue { i64, i1 } %0, 0
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%3 = tail call { i64, i1 } @llvm.uadd.with.overflow.i64(i64 %2, i64 %c)
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%4 = extractvalue { i64, i1 } %3, 1
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%5 = extractvalue { i64, i1 } %3, 0
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%6 = or i1 %1, %4
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%7 = zext i1 %6 to i64
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store i64 %7, ptr %ovf, align 8
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ret i64 %5
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}

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