- Fold analysis into getAllocationHints

Author: perlfu

llvm/lib/Target/AMDGPU/AMDGPU.h

@@ -549,9 +549,6 @@ extern char &GCNRewritePartialRegUsesID;
 void initializeAMDGPUWaitSGPRHazardsLegacyPass(PassRegistry &);
 extern char &AMDGPUWaitSGPRHazardsLegacyID;
 
-void initializeAMDGPUMarkSGPRHazardRegsLegacyPass(PassRegistry &);
-extern char &AMDGPUMarkSGPRHazardRegsLegacyID;
-
 namespace AMDGPU {
 enum TargetIndex {
   TI_CONSTDATA_START,

llvm/lib/Target/AMDGPU/AMDGPUMarkSGPRHazardRegs.cpp

@@ -23,7 +23,6 @@
 #include "AMDGPUIGroupLP.h"
 #include "AMDGPUISelDAGToDAG.h"
 #include "AMDGPUMacroFusion.h"
-#include "AMDGPUMarkSGPRHazardRegs.h"
 #include "AMDGPUPerfHintAnalysis.h"
 #include "AMDGPUPreloadKernArgProlog.h"
 #include "AMDGPURemoveIncompatibleFunctions.h"
@@ -568,7 +567,6 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUTarget() {
   initializeAMDGPUPreloadKernArgPrologLegacyPass(*PR);
   initializeAMDGPUWaitSGPRHazardsLegacyPass(*PR);
   initializeAMDGPUPreloadKernelArgumentsLegacyPass(*PR);
-  initializeAMDGPUMarkSGPRHazardRegsLegacyPass(*PR);
 }
 
 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
@@ -1669,7 +1667,6 @@ bool GCNPassConfig::addRegAssignAndRewriteOptimized() {
 
   addPass(&GCNPreRALongBranchRegID);
 
-  addPass(&AMDGPUMarkSGPRHazardRegsLegacyID);
   addPass(createSGPRAllocPass(true));
 
   // Commit allocated register changes. This is mostly necessary because too

llvm/lib/Target/AMDGPU/AMDGPUMarkSGPRHazardRegs.h

@@ -84,7 +84,6 @@ add_llvm_target(AMDGPUCodeGen
   AMDGPUIGroupLP.cpp
   AMDGPUMCResourceInfo.cpp
   AMDGPUMarkLastScratchLoad.cpp
-  AMDGPUMarkSGPRHazardRegs.cpp
   AMDGPUMIRFormatter.cpp
   AMDGPUPerfHintAnalysis.cpp
   AMDGPUPostLegalizerCombiner.cpp

llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp

@@ -3864,10 +3864,26 @@ bool SIRegisterInfo::getRegAllocationHints(Register VirtReg,
   if (!isSGPRClass(RC))
     return BaseImplRetVal;
 
+  // Exit without an avoidance strategy
   const unsigned Strategy = getSGPRHazardAvoidanceStrategy(MF);
   if (!Strategy)
     return BaseImplRetVal;
 
+  // Register has a hazard if it is SGPR used by VALU
+  DenseMap<Register, bool> HazardRegs;
+  auto HasSGPRHazard = [&MRI, TRI, &HazardRegs](Register Reg) {
+    const auto *RC = MRI.getRegClass(Reg);
+    if (!RC || !TRI->isSGPRClass(RC))
+      return false;
+    if (!HazardRegs.contains(Reg)) {
+      HazardRegs[Reg] = llvm::any_of(
+          MRI.reg_nodbg_operands(Reg), [](const MachineOperand &MO) {
+            return MO.isUse() && SIInstrInfo::isVALU(*MO.getParent());
+          });
+    }
+    return HazardRegs[Reg];
+  };
+
   SmallSet<MCPhysReg, 4> CopyHints;
   CopyHints.insert(Hints.begin(), Hints.end());
 
@@ -3883,7 +3899,7 @@ bool SIRegisterInfo::getRegAllocationHints(Register VirtReg,
 
   // V1: simply reverse allocation order, mean 23% reduction in hazards
   if (Strategy == 1) {
-    if (FuncInfo->checkFlag(VirtReg, AMDGPU::VirtRegFlag::SGPR_HAZARD_REG)) {
+    if (HasSGPRHazard(VirtReg)) {
       for (MCPhysReg PhysReg : reverse(Order))
         AddHint(PhysReg);
     } else {
@@ -3906,8 +3922,7 @@ bool SIRegisterInfo::getRegAllocationHints(Register VirtReg,
       LiveIntervalUnion &LIU = LiveUnions[Unit];
       for (const LiveInterval *LI : LIU.getMap()) {
         Intervals.insert(LI);
-        if (FuncInfo->checkFlag(LI->reg(),
-                                AMDGPU::VirtRegFlag::SGPR_HAZARD_REG)) {
+        if (HasSGPRHazard(LI->reg())) {
           IsHazard = true;
           // Break here as we only care about interval count for non-hazard regs
           break;
@@ -3927,8 +3942,7 @@ bool SIRegisterInfo::getRegAllocationHints(Register VirtReg,
   // V2: weight the entire order based on hazard free usage, mean 30% reduction
   // in hazards
   if (Strategy == 2) {
-    bool VRegIsHazard =
-        FuncInfo->checkFlag(VirtReg, AMDGPU::VirtRegFlag::SGPR_HAZARD_REG);
+    bool VRegIsHazard = HasSGPRHazard(VirtReg);
     SmallVector<MCPhysReg> NewOrder(Order);
     std::sort(NewOrder.begin(), NewOrder.end(), [&](MCPhysReg A, MCPhysReg B) {
       return VRegIsHazard ? IntervalCount[A] < IntervalCount[B]
@@ -3969,7 +3983,7 @@ bool SIRegisterInfo::getRegAllocationHints(Register VirtReg,
     }
   }
 
-  if (FuncInfo->checkFlag(VirtReg, AMDGPU::VirtRegFlag::SGPR_HAZARD_REG)) {
+  if (HasSGPRHazard(VirtReg)) {
     // Reorder allocations based on usage, so least used will be reused first.
     // This means least used regs are touched by hazards first.
     std::sort(Allocated.begin(), Allocated.end(),

llvm/lib/Target/AMDGPU/CMakeLists.txt

@@ -350,7 +350,6 @@
 ; GCN-O1-NEXT:        SI Whole Quad Mode
 ; GCN-O1-NEXT:        SI optimize exec mask operations pre-RA
 ; GCN-O1-NEXT:        AMDGPU Pre-RA Long Branch Reg
-; GCN-O1-NEXT:        AMDGPU Mark Hazard SGPRs
 ; GCN-O1-NEXT:        Machine Natural Loop Construction
 ; GCN-O1-NEXT:        Machine Block Frequency Analysis
 ; GCN-O1-NEXT:        Debug Variable Analysis
@@ -661,7 +660,6 @@
 ; GCN-O1-OPTS-NEXT:        SI Whole Quad Mode
 ; GCN-O1-OPTS-NEXT:        SI optimize exec mask operations pre-RA
 ; GCN-O1-OPTS-NEXT:        AMDGPU Pre-RA Long Branch Reg
-; GCN-O1-OPTS-NEXT:        AMDGPU Mark Hazard SGPRs
 ; GCN-O1-OPTS-NEXT:        Machine Natural Loop Construction
 ; GCN-O1-OPTS-NEXT:        Machine Block Frequency Analysis
 ; GCN-O1-OPTS-NEXT:        Debug Variable Analysis
@@ -978,7 +976,6 @@
 ; GCN-O2-NEXT:        SI optimize exec mask operations pre-RA
 ; GCN-O2-NEXT:        SI Form memory clauses
 ; GCN-O2-NEXT:        AMDGPU Pre-RA Long Branch Reg
-; GCN-O2-NEXT:        AMDGPU Mark Hazard SGPRs
 ; GCN-O2-NEXT:        Machine Natural Loop Construction
 ; GCN-O2-NEXT:        Machine Block Frequency Analysis
 ; GCN-O2-NEXT:        Debug Variable Analysis
@@ -1308,7 +1305,6 @@
 ; GCN-O3-NEXT:        SI optimize exec mask operations pre-RA
 ; GCN-O3-NEXT:        SI Form memory clauses
 ; GCN-O3-NEXT:        AMDGPU Pre-RA Long Branch Reg
-; GCN-O3-NEXT:        AMDGPU Mark Hazard SGPRs
 ; GCN-O3-NEXT:        Machine Natural Loop Construction
 ; GCN-O3-NEXT:        Machine Block Frequency Analysis
 ; GCN-O3-NEXT:        Debug Variable Analysis