Update implementation to match proposal

lenary · lenary · commit c70f679f3285 · 2025-03-19T13:51:43.000-07:00
diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -3173,46 +3173,44 @@ bool RISCVAsmParser::parseDirectiveOption() {
     return false;
   }
 
-  if (Option == "rvc") {
+  if (Option == "exact") {
     if (Parser.parseEOL())
       return true;
 
-    getTargetStreamer().emitDirectiveOptionRVC();
-    setFeatureBits(RISCV::FeatureStdExtC, "c");
-    clearFeatureBits(RISCV::FeatureDisableAsmCompression,
-                     "disable-asm-compression");
+    getTargetStreamer().emitDirectiveOptionExact();
+    setFeatureBits(RISCV::FeatureExactAssembly,
+                   "exact-asm");
+    clearFeatureBits(RISCV::FeatureRelax, "relax");
     return false;
   }
 
-  if (Option == "norvc") {
+  if (Option == "noexact") {
     if (Parser.parseEOL())
       return true;
 
-    getTargetStreamer().emitDirectiveOptionNoRVC();
-    clearFeatureBits(RISCV::FeatureStdExtC, "c");
-    clearFeatureBits(RISCV::FeatureStdExtZca, "zca");
-    setFeatureBits(RISCV::FeatureDisableAsmCompression,
-                   "disable-asm-compression");
+    getTargetStreamer().emitDirectiveOptionNoExact();
+    clearFeatureBits(RISCV::FeatureExactAssembly,
+                     "exact-asm");
+    setFeatureBits(RISCV::FeatureRelax, "relax");
     return false;
   }
 
-  if (Option == "autocompress") {
+  if (Option == "rvc") {
     if (Parser.parseEOL())
       return true;
 
-    getTargetStreamer().emitDirectiveOptionAutoCompress();
-    clearFeatureBits(RISCV::FeatureDisableAsmCompression,
-                     "disable-asm-compression");
+    getTargetStreamer().emitDirectiveOptionRVC();
+    setFeatureBits(RISCV::FeatureStdExtC, "c");
     return false;
   }
 
-  if (Option == "noautocompress") {
+  if (Option == "norvc") {
     if (Parser.parseEOL())
       return true;
 
-    getTargetStreamer().emitDirectiveOptionNoAutoCompress();
-    setFeatureBits(RISCV::FeatureDisableAsmCompression,
-                   "disable-asm-compression");
+    getTargetStreamer().emitDirectiveOptionNoRVC();
+    clearFeatureBits(RISCV::FeatureStdExtC, "c");
+    clearFeatureBits(RISCV::FeatureStdExtZca, "zca");
     return false;
   }
 
@@ -3254,8 +3252,8 @@ bool RISCVAsmParser::parseDirectiveOption() {
 
   // Unknown option.
   Warning(Parser.getTok().getLoc(), "unknown option, expected 'push', 'pop', "
-                                    "'rvc', 'norvc', 'arch', 'relax' or "
-                                    "'norelax'");
+                                    "'rvc', 'norvc', 'arch', 'relax', 'norelax', "
+                                    "'exact' or 'noexact'");
   Parser.eatToEndOfStatement();
   return false;
 }
@@ -3466,11 +3464,12 @@ bool RISCVAsmParser::parseDirectiveVariantCC() {
 void RISCVAsmParser::emitToStreamer(MCStreamer &S, const MCInst &Inst) {
   MCInst CInst;
   bool Res = false;
-  if (!getSTI().hasFeature(RISCV::FeatureDisableAsmCompression))
-    Res = RISCVRVC::compress(CInst, Inst, getSTI());
+  const MCSubtargetInfo &STI = getSTI();
+  if (!STI.hasFeature(RISCV::FeatureExactAssembly))
+    Res = RISCVRVC::compress(CInst, Inst, STI);
   if (Res)
     ++RISCVNumInstrsCompressed;
-  S.emitInstruction((Res ? CInst : Inst), getSTI());
+  S.emitInstruction((Res ? CInst : Inst), STI);
 }
 
 void RISCVAsmParser::emitLoadImm(MCRegister DestReg, int64_t Value,
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
@@ -344,6 +344,10 @@ std::pair<bool, bool> RISCVAsmBackend::relaxLEB128(const MCAssembler &Asm,
 // Given a compressed control flow instruction this function returns
 // the expanded instruction.
 unsigned RISCVAsmBackend::getRelaxedOpcode(unsigned Op) const {
+  // Disable relaxation if FeatureExactAssembly
+  if (STI.hasFeature(RISCV::FeatureExactAssembly))
+    return Op;
+
   switch (Op) {
   default:
     return Op;
@@ -371,6 +375,12 @@ unsigned RISCVAsmBackend::getRelaxedOpcode(unsigned Op) const {
 
 bool RISCVAsmBackend::mayNeedRelaxation(const MCInst &Inst,
                                         const MCSubtargetInfo &STI) const {
+  // This function has access to two STIs, the member of the AsmBackend, and the
+  // one passed as an argument. The latter is more specific, so we query it for
+  // specific features.
+  if (STI.hasFeature(RISCV::FeatureExactAssembly))
+    return false;
+
   return getRelaxedOpcode(Inst.getOpcode()) != Inst.getOpcode();
 }
 
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp
@@ -53,8 +53,8 @@ void RISCVTargetELFStreamer::emitDirectiveOptionPIC() {}
 void RISCVTargetELFStreamer::emitDirectiveOptionNoPIC() {}
 void RISCVTargetELFStreamer::emitDirectiveOptionRVC() {}
 void RISCVTargetELFStreamer::emitDirectiveOptionNoRVC() {}
-void RISCVTargetELFStreamer::emitDirectiveOptionAutoCompress() {}
-void RISCVTargetELFStreamer::emitDirectiveOptionNoAutoCompress() {}
+void RISCVTargetELFStreamer::emitDirectiveOptionExact() {}
+void RISCVTargetELFStreamer::emitDirectiveOptionNoExact() {}
 void RISCVTargetELFStreamer::emitDirectiveOptionRelax() {}
 void RISCVTargetELFStreamer::emitDirectiveOptionNoRelax() {}
 
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.h
@@ -62,8 +62,8 @@ class RISCVTargetELFStreamer : public RISCVTargetStreamer {
   void emitDirectiveOptionNoPIC() override;
   void emitDirectiveOptionRVC() override;
   void emitDirectiveOptionNoRVC() override;
-  void emitDirectiveOptionAutoCompress() override;
-  void emitDirectiveOptionNoAutoCompress() override;
+  void emitDirectiveOptionExact() override;
+  void emitDirectiveOptionNoExact() override;
   void emitDirectiveOptionRelax() override;
   void emitDirectiveOptionNoRelax() override;
   void emitDirectiveVariantCC(MCSymbol &Symbol) override;
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
@@ -39,8 +39,8 @@ void RISCVTargetStreamer::emitDirectiveOptionPIC() {}
 void RISCVTargetStreamer::emitDirectiveOptionNoPIC() {}
 void RISCVTargetStreamer::emitDirectiveOptionRVC() {}
 void RISCVTargetStreamer::emitDirectiveOptionNoRVC() {}
-void RISCVTargetStreamer::emitDirectiveOptionAutoCompress() {}
-void RISCVTargetStreamer::emitDirectiveOptionNoAutoCompress() {}
+void RISCVTargetStreamer::emitDirectiveOptionExact() {}
+void RISCVTargetStreamer::emitDirectiveOptionNoExact() {}
 void RISCVTargetStreamer::emitDirectiveOptionRelax() {}
 void RISCVTargetStreamer::emitDirectiveOptionNoRelax() {}
 void RISCVTargetStreamer::emitDirectiveOptionArch(
@@ -127,12 +127,12 @@ void RISCVTargetAsmStreamer::emitDirectiveOptionNoRVC() {
   OS << "\t.option\tnorvc\n";
 }
 
-void RISCVTargetAsmStreamer::emitDirectiveOptionAutoCompress() {
-  OS << "\t.option\tautocompress\n";
+void RISCVTargetAsmStreamer::emitDirectiveOptionExact() {
+  OS << "\t.option\texact\n";
 }
 
-void RISCVTargetAsmStreamer::emitDirectiveOptionNoAutoCompress() {
-  OS << "\t.option\tnoautocompress\n";
+void RISCVTargetAsmStreamer::emitDirectiveOptionNoExact() {
+  OS << "\t.option\tnoexact\n";
 }
 
 void RISCVTargetAsmStreamer::emitDirectiveOptionRelax() {
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.h
@@ -47,8 +47,8 @@ class RISCVTargetStreamer : public MCTargetStreamer {
   virtual void emitDirectiveOptionNoPIC();
   virtual void emitDirectiveOptionRVC();
   virtual void emitDirectiveOptionNoRVC();
-  virtual void emitDirectiveOptionAutoCompress();
-  virtual void emitDirectiveOptionNoAutoCompress();
+  virtual void emitDirectiveOptionExact();
+  virtual void emitDirectiveOptionNoExact();
   virtual void emitDirectiveOptionRelax();
   virtual void emitDirectiveOptionNoRelax();
   virtual void emitDirectiveOptionArch(ArrayRef<RISCVOptionArchArg> Args);
@@ -86,8 +86,8 @@ class RISCVTargetAsmStreamer : public RISCVTargetStreamer {
   void emitDirectiveOptionNoPIC() override;
   void emitDirectiveOptionRVC() override;
   void emitDirectiveOptionNoRVC() override;
-  void emitDirectiveOptionAutoCompress() override;
-  void emitDirectiveOptionNoAutoCompress() override;
+  void emitDirectiveOptionExact() override;
+  void emitDirectiveOptionNoExact() override;
   void emitDirectiveOptionRelax() override;
   void emitDirectiveOptionNoRelax() override;
   void emitDirectiveOptionArch(ArrayRef<RISCVOptionArchArg> Args) override;
diff --git a/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp b/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
@@ -255,7 +255,7 @@ bool RISCVAsmPrinter::EmitToStreamer(MCStreamer &S, const MCInst &Inst,
                                      const MCSubtargetInfo &SubtargetInfo) {
   MCInst CInst;
   bool Res = false;
-  if (!SubtargetInfo.hasFeature(RISCV::FeatureDisableAsmCompression))
+  if (!SubtargetInfo.hasFeature(RISCV::FeatureExactAssembly))
     Res = RISCVRVC::compress(CInst, Inst, SubtargetInfo);
   if (Res)
     ++RISCVNumInstrsCompressed;
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -1470,9 +1470,9 @@ def FeatureRelax
     : SubtargetFeature<"relax", "EnableLinkerRelax", "true",
                        "Enable Linker relaxation.">;
 
-def FeatureDisableAsmCompression
-    : SubtargetFeature<"disable-asm-compression", "EnableAsmCompression", "false",
-                       "Disable Automatic Assembly Compression.">;
+def FeatureExactAssembly
+    : SubtargetFeature<"exact-asm", "EnableExactAssembly", "true",
+                       "Enable Exact Assembly (Disables Compression and Relaxation)">;
 
 foreach i = {1-31} in
   def FeatureReserveX#i :
diff --git a/llvm/test/MC/RISCV/option-exact-compression.s b/llvm/test/MC/RISCV/option-exact-compression.s
@@ -21,11 +21,13 @@
 # RUN:   | FileCheck -check-prefixes=CHECK-BYTES,CHECK-INST %s
 
 
-# `.option (no)autocompress` enables and disables instruction compression in the
-# assembler, without changing the current architecture.
-#
-# The default is as if `.option autocompress` has been specified, that is, the
-# assembler compresses by default.
+## `.option exact` disables a variety of assembler behaviour:
+## - automatic compression
+## - branch relaxation (of short branches to longer equivalent sequences)
+## - linker relaxation (emitting R_RISCV_RELAX)
+## `.option noexact` enables these behaviours again. It is also the default.
+
+## This test only checks the automatic compression part of this behaviour.
 
 # CHECK-BYTES: 4108
 # CHECK-INST: c.lw a0, 0(a0)
@@ -39,8 +41,8 @@ lw a0, 0(a0)
 # CHECK: # encoding: [0x08,0x41]
 c.lw a0, 0(a0)
 
-# CHECK: .option noautocompress
-.option noautocompress
+# CHECK: .option exact
+.option exact
 
 # CHECK-BYTES: 00052503
 # CHECK-INST: lw a0, 0(a0)
@@ -54,8 +56,8 @@ lw a0, 0(a0)
 # CHECK: # encoding: [0x08,0x41]
 c.lw a0, 0(a0)
 
-# CHECK: .option autocompress
-.option autocompress
+# CHECK: .option noexact
+.option noexact
 
 # CHECK-BYTES: 4108
 # CHECK-INST: c.lw a0, 0(a0)
diff --git a/llvm/test/MC/RISCV/option-exact-relaxation.s b/llvm/test/MC/RISCV/option-exact-relaxation.s
@@ -0,0 +1,74 @@
+# RUN: llvm-mc -triple riscv32 -show-encoding -mattr=+relax %s \
+# RUN:   | FileCheck -check-prefixes=CHECK-ASM %s
+# RUN: llvm-mc -triple riscv32 -filetype=obj -mattr=+relax %s \
+# RUN:   | llvm-objdump  --triple=riscv32 --no-show-raw-insn -dr - \
+# RUN:   | FileCheck -check-prefixes=CHECK-OBJDUMP %s
+
+# RUN: llvm-mc -triple riscv64 -show-encoding -mattr=+relax %s \
+# RUN:   | FileCheck -check-prefixes=CHECK-ASM %s
+# RUN: llvm-mc -triple riscv64 -filetype=obj -mattr=+relax %s \
+# RUN:   | llvm-objdump  --triple=riscv64 --no-show-raw-insn -dr - \
+# RUN:   | FileCheck -check-prefixes=CHECK-OBJDUMP %s
+
+## `.option exact` disables a variety of assembler behaviour:
+## - automatic compression
+## - branch relaxation (of short branches to longer equivalent sequences)
+## - linker relaxation (emitting R_RISCV_RELAX)
+## `.option noexact` enables these behaviours again. It is also the default.
+
+## This test only checks the branch and linker relaxation part of this behaviour.
+
+
+
+# CHECK-ASM: call undefined
+# CHECK-ASM-NEXT: fixup A - offset: 0, value: undefined, kind: fixup_riscv_call_plt
+# CHECK-ASM-NEXT: fixup B - offset: 0, value: 0, kind: fixup_riscv_relax
+# CHECK-OBJDUMP: auipc ra, 0x0
+# CHECK-OBJDUMP-NEXT: R_RISCV_CALL_PLT undefined
+# CHECK-OBJDUMP-NEXT: R_RISCV_RELAX *ABS*
+# CHECK-OBJDUMP-NEXT: jalr ra
+call undefined@plt
+
+# CHECK-ASM: beq a0, a1, undefined
+# CHECK-ASM-NEXT: fixup A - offset: 0, value: undefined, kind: fixup_riscv_branch
+# CHECK-OBJDUMP: bne a0, a1, 0x10
+# CHECK-OBJDUMP-NEXT: j 0xc
+# CHECK-OBJDUMP-NEXT: R_RISCV_JAL undefined
+beq a0, a1, undefined
+
+# CHECK-ASM: .option exact
+.option exact
+
+# CHECK-ASM: call undefined
+# CHECK-ASM-NEXT: fixup A - offset: 0, value: undefined, kind: fixup_riscv_call_plt
+# CHECK-ASM-NOT: fixup_riscv_relax
+# CHECK-OBJDUMP: auipc ra, 0x0
+# CHECK-OBJDUMP-NEXT: R_RISCV_CALL_PLT undefined
+# CHECK-OBJDUMP-NOT: R_RISCV_RELAX
+# CHECK-OBJDUMP-NEXT: jalr ra
+call undefined@plt
+
+# CHECK-ASM: beq a0, a1, undefined
+# CHECK-ASM-NEXT: fixup A - offset: 0, value: undefined, kind: fixup_riscv_branch
+# CHECK-OBJDUMP: beq a0, a1, 0x18
+# CHECK-OBJDUMP-NEXT: R_RISCV_BRANCH undefined
+beq a0, a1, undefined
+
+# CHECK-ASM: .option noexact
+.option noexact
+
+# CHECK-ASM: call undefined
+# CHECK-ASM-NEXT: fixup A - offset: 0, value: undefined, kind: fixup_riscv_call_plt
+# CHECK-ASM-NEXT: fixup B - offset: 0, value: 0, kind: fixup_riscv_relax
+# CHECK-OBJDUMP: auipc ra, 0x0
+# CHECK-OBJDUMP-NEXT: R_RISCV_CALL_PLT undefined
+# CHECK-OBJDUMP-NEXT: R_RISCV_RELAX *ABS*
+# CHECK-OBJDUMP-NEXT: jalr ra
+call undefined@plt
+
+# CHECK-ASM: beq a0, a1, undefined
+# CHECK-ASM-NEXT: fixup A - offset: 0, value: undefined, kind: fixup_riscv_branch
+# CHECK-OBJDUMP: bne a0, a1, 0x2c
+# CHECK-OBJDUMP-NEXT: j 0x28
+# CHECK-OBJDUMP-NEXT: R_RISCV_JAL undefined
+beq a0, a1, undefined
