Use tuimm

Author: svs-quic

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

@@ -1845,16 +1845,6 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
     CurDAG->RemoveDeadNode(Node);
     return;
   }
-  case RISCVISD::QC_SETWMI: {
-    SDValue Chain = Node->getOperand(0);
-    SDVTList VTs = Node->getVTList();
-    SDValue Ops[] = {Node->getOperand(1), Node->getOperand(2),
-                     Node->getOperand(3), Node->getOperand(4), Chain};
-    MachineSDNode *New = CurDAG->getMachineNode(RISCV::QC_SETWMI, DL, VTs, Ops);
-    CurDAG->setNodeMemRefs(New, {cast<MemSDNode>(Node)->getMemOperand()});
-    ReplaceNode(Node, New);
-    return;
-  }
   case ISD::INTRINSIC_WO_CHAIN: {
     unsigned IntNo = Node->getConstantOperandVal(0);
     switch (IntNo) {

llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td

@@ -35,6 +35,8 @@ def uimm5nonzero : RISCVOp<XLenVT>,
   }];
 }
 
+def tuimm5nonzero : TImmLeaf<XLenVT, [{return (Imm != 0) && isUInt<5>(Imm);}]>;
+
 def uimm5gt3 : RISCVOp<XLenVT>, ImmLeaf<XLenVT,
   [{return (Imm > 3) && isUInt<5>(Imm);}]> {
   let ParserMatchClass = UImmAsmOperand<5, "GT3">;
@@ -100,6 +102,8 @@ def uimm5slist : RISCVOp<XLenVT>, ImmLeaf<XLenVT,
   }];
 }
 
+def tuimm7_lsb00 : TImmLeaf<XLenVT,[{return isShiftedUInt<5, 2>(Imm);}]>;
+
 def uimm10 : RISCVUImmLeafOp<10>;
 
 def uimm11 : RISCVUImmLeafOp<11>;
@@ -1574,6 +1578,11 @@ def : QCISELECTIICCPat <SETEQ,  QC_SELECTIIEQ>;
 def : QCISELECTIICCPat <SETNE,  QC_SELECTIINE>;
 } // Predicates = [HasVendorXqcics, IsRV32]
 
+let Predicates = [HasVendorXqcilsm, IsRV32] in {
+def : Pat<(qc_setwmi i32:$rd, GPR:$rs1, tuimm5nonzero:$uimm5, tuimm7_lsb00:$uimm7),
+          (QC_SETWMI i32:$rd, GPR:$rs1, tuimm5nonzero:$uimm5, tuimm7_lsb00:$uimm7)>;
+} // Predicates = [HasVendorXqcilsm, IsRV32]
+
 //===----------------------------------------------------------------------===/i
 // Compress Instruction tablegen backend.
 //===----------------------------------------------------------------------===//

llvm/lib/Target/RISCV/RISCVSelectionDAGInfo.cpp

@@ -82,7 +82,7 @@ SDValue RISCVSelectionDAGInfo::EmitTargetCodeForMemset(
   uint64_t NumberOfBytesToWrite = ConstantSize->getZExtValue();
 
   // Do this only if it is word aligned and we write multiple of 4 bytes.
-  if (!(Alignment.value() >= 4) || !((NumberOfBytesToWrite & 3) == 0))
+  if (!(Alignment >= 4) || !((NumberOfBytesToWrite & 3) == 0))
     return SDValue();
 
   SmallVector<SDValue, 8> OutChains;