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6 files changed

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‎llvm/test/CodeGen/AMDGPU/debug-value.ll‎

Lines changed: 1 addition & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1,10 +1,4 @@
1-
<<<<<<< HEAD
2-
; RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -experimental-debug-variable-locations=false -amdgpu-codegenprepare-break-large-phis=0 < %s | FileCheck %s
3-
||||||| 5050a1507116
4-
; RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -amdgpu-codegenprepare-break-large-phis=0 < %s | FileCheck %s
5-
=======
6-
; RUN: llc -mtriple=amdgcn-amd-amdhsa -amdgpu-codegenprepare-break-large-phis=0 < %s | FileCheck %s
7-
>>>>>>> 5f20518f5b4734d01848dfe44d24aed195dc2043
1+
; RUN: llc -mtriple=amdgcn-amd-amdhsa -experimental-debug-variable-locations=false -amdgpu-codegenprepare-break-large-phis=0 < %s | FileCheck %s
82

93
%struct.wombat = type { [4 x i32], [4 x i32], [4 x i32] }
104

‎llvm/test/CodeGen/AMDGPU/debug-value2.ll‎

Lines changed: 1 addition & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1,10 +1,4 @@
1-
<<<<<<< HEAD
2-
; RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -experimental-debug-variable-locations=false < %s | FileCheck %s
3-
||||||| 5050a1507116
4-
; RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs < %s | FileCheck %s
5-
=======
6-
; RUN: llc -mtriple=amdgcn-amd-amdhsa < %s | FileCheck %s
7-
>>>>>>> 5f20518f5b4734d01848dfe44d24aed195dc2043
1+
; RUN: llc -mtriple=amdgcn-amd-amdhsa -experimental-debug-variable-locations=false < %s | FileCheck %s
82

93
%struct.ShapeData = type { <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, i32, i32, i64, <4 x float>, i32, i8, i8, i16, i32, i32 }
104

‎llvm/test/CodeGen/AMDGPU/frame-setup-without-sgpr-to-vgpr-spills.ll‎

Lines changed: 4 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -1,17 +1,8 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2-
<<<<<<< HEAD
3-
; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs -amdgpu-spill-sgpr-to-vgpr=true -amdgpu-spill-cfi-saved-regs=false < %s | FileCheck -check-prefixes=NO-CFI-SAVES-SPILL-TO-VGPR %s
4-
; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs -amdgpu-spill-sgpr-to-vgpr=true -amdgpu-spill-cfi-saved-regs=true < %s | FileCheck -check-prefixes=CFI-SAVES-SPILL-TO-VGPR %s
5-
; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs -amdgpu-spill-sgpr-to-vgpr=false -amdgpu-spill-cfi-saved-regs=false < %s | FileCheck -check-prefixes=NO-CFI-SAVES-NO-SPILL-TO-VGPR %s
6-
; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs -amdgpu-spill-sgpr-to-vgpr=false -amdgpu-spill-cfi-saved-regs=true < %s | FileCheck -check-prefixes=CFI-SAVES-NO-SPILL-TO-VGPR %s
7-
8-
||||||| 5050a1507116
9-
; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs -amdgpu-spill-sgpr-to-vgpr=true < %s | FileCheck -check-prefix=SPILL-TO-VGPR %s
10-
; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs -amdgpu-spill-sgpr-to-vgpr=false < %s | FileCheck -check-prefix=NO-SPILL-TO-VGPR %s
11-
=======
12-
; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -amdgpu-spill-sgpr-to-vgpr=true < %s | FileCheck -check-prefix=SPILL-TO-VGPR %s
13-
; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -amdgpu-spill-sgpr-to-vgpr=false < %s | FileCheck -check-prefix=NO-SPILL-TO-VGPR %s
14-
>>>>>>> 5f20518f5b4734d01848dfe44d24aed195dc2043
2+
; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -amdgpu-spill-sgpr-to-vgpr=true -amdgpu-spill-cfi-saved-regs=false < %s | FileCheck -check-prefixes=NO-CFI-SAVES-SPILL-TO-VGPR %s
3+
; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -amdgpu-spill-sgpr-to-vgpr=true -amdgpu-spill-cfi-saved-regs=true < %s | FileCheck -check-prefixes=CFI-SAVES-SPILL-TO-VGPR %s
4+
; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -amdgpu-spill-sgpr-to-vgpr=false -amdgpu-spill-cfi-saved-regs=false < %s | FileCheck -check-prefixes=NO-CFI-SAVES-NO-SPILL-TO-VGPR %s
5+
; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -amdgpu-spill-sgpr-to-vgpr=false -amdgpu-spill-cfi-saved-regs=true < %s | FileCheck -check-prefixes=CFI-SAVES-NO-SPILL-TO-VGPR %s
156

167
; Check frame setup where SGPR spills to VGPRs are disabled or enabled.
178

‎llvm/test/CodeGen/AMDGPU/global-load-xcnt.ll‎

Lines changed: 36 additions & 132 deletions
Original file line numberDiff line numberDiff line change
@@ -124,65 +124,33 @@ define i32 @test_v64i32_load_store(ptr addrspace(1) %ptr, i32 %idx, ptr addrspac
124124
; GCN-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
125125
; GCN-SDAG-NEXT: s_wait_kmcnt 0x0
126126
; GCN-SDAG-NEXT: s_clause 0xd
127-
<<<<<<< HEAD
128-
; GCN-SDAG-NEXT: scratch_store_b32 off, v40, s32 offset:52
129-
; GCN-SDAG-NEXT: ; meta instruction
130-
; GCN-SDAG-NEXT: scratch_store_b32 off, v41, s32 offset:48
131-
; GCN-SDAG-NEXT: ; meta instruction
132-
; GCN-SDAG-NEXT: scratch_store_b32 off, v42, s32 offset:44
133-
; GCN-SDAG-NEXT: ; meta instruction
134-
; GCN-SDAG-NEXT: scratch_store_b32 off, v43, s32 offset:40
135-
; GCN-SDAG-NEXT: ; meta instruction
136-
; GCN-SDAG-NEXT: scratch_store_b32 off, v44, s32 offset:36
137-
; GCN-SDAG-NEXT: ; meta instruction
138-
; GCN-SDAG-NEXT: scratch_store_b32 off, v45, s32 offset:32
139-
; GCN-SDAG-NEXT: ; meta instruction
140-
; GCN-SDAG-NEXT: scratch_store_b32 off, v56, s32 offset:28
141-
; GCN-SDAG-NEXT: ; meta instruction
142-
; GCN-SDAG-NEXT: scratch_store_b32 off, v57, s32 offset:24
143-
; GCN-SDAG-NEXT: ; meta instruction
144-
; GCN-SDAG-NEXT: scratch_store_b32 off, v58, s32 offset:20
145-
; GCN-SDAG-NEXT: ; meta instruction
146-
; GCN-SDAG-NEXT: scratch_store_b32 off, v59, s32 offset:16
147-
; GCN-SDAG-NEXT: ; meta instruction
148-
; GCN-SDAG-NEXT: scratch_store_b32 off, v60, s32 offset:12
149-
; GCN-SDAG-NEXT: ; meta instruction
150-
; GCN-SDAG-NEXT: scratch_store_b32 off, v61, s32 offset:8
151-
; GCN-SDAG-NEXT: ; meta instruction
152-
; GCN-SDAG-NEXT: scratch_store_b32 off, v62, s32 offset:4
153-
; GCN-SDAG-NEXT: ; meta instruction
154-
; GCN-SDAG-NEXT: scratch_store_b32 off, v63, s32
155-
||||||| 5050a1507116
156-
; GCN-SDAG-NEXT: scratch_store_b32 off, v40, s32 offset:52
157-
; GCN-SDAG-NEXT: scratch_store_b32 off, v41, s32 offset:48
158-
; GCN-SDAG-NEXT: scratch_store_b32 off, v42, s32 offset:44
159-
; GCN-SDAG-NEXT: scratch_store_b32 off, v43, s32 offset:40
160-
; GCN-SDAG-NEXT: scratch_store_b32 off, v44, s32 offset:36
161-
; GCN-SDAG-NEXT: scratch_store_b32 off, v45, s32 offset:32
162-
; GCN-SDAG-NEXT: scratch_store_b32 off, v56, s32 offset:28
163-
; GCN-SDAG-NEXT: scratch_store_b32 off, v57, s32 offset:24
164-
; GCN-SDAG-NEXT: scratch_store_b32 off, v58, s32 offset:20
165-
; GCN-SDAG-NEXT: scratch_store_b32 off, v59, s32 offset:16
166-
; GCN-SDAG-NEXT: scratch_store_b32 off, v60, s32 offset:12
167-
; GCN-SDAG-NEXT: scratch_store_b32 off, v61, s32 offset:8
168-
; GCN-SDAG-NEXT: scratch_store_b32 off, v62, s32 offset:4
169-
; GCN-SDAG-NEXT: scratch_store_b32 off, v63, s32
170-
=======
171127
; GCN-SDAG-NEXT: scratch_store_b32 off, v40, s32 offset:52 scope:SCOPE_SE
128+
; GCN-SDAG-NEXT: ; meta instruction
172129
; GCN-SDAG-NEXT: scratch_store_b32 off, v41, s32 offset:48 scope:SCOPE_SE
130+
; GCN-SDAG-NEXT: ; meta instruction
173131
; GCN-SDAG-NEXT: scratch_store_b32 off, v42, s32 offset:44 scope:SCOPE_SE
132+
; GCN-SDAG-NEXT: ; meta instruction
174133
; GCN-SDAG-NEXT: scratch_store_b32 off, v43, s32 offset:40 scope:SCOPE_SE
134+
; GCN-SDAG-NEXT: ; meta instruction
175135
; GCN-SDAG-NEXT: scratch_store_b32 off, v44, s32 offset:36 scope:SCOPE_SE
136+
; GCN-SDAG-NEXT: ; meta instruction
176137
; GCN-SDAG-NEXT: scratch_store_b32 off, v45, s32 offset:32 scope:SCOPE_SE
138+
; GCN-SDAG-NEXT: ; meta instruction
177139
; GCN-SDAG-NEXT: scratch_store_b32 off, v56, s32 offset:28 scope:SCOPE_SE
140+
; GCN-SDAG-NEXT: ; meta instruction
178141
; GCN-SDAG-NEXT: scratch_store_b32 off, v57, s32 offset:24 scope:SCOPE_SE
142+
; GCN-SDAG-NEXT: ; meta instruction
179143
; GCN-SDAG-NEXT: scratch_store_b32 off, v58, s32 offset:20 scope:SCOPE_SE
144+
; GCN-SDAG-NEXT: ; meta instruction
180145
; GCN-SDAG-NEXT: scratch_store_b32 off, v59, s32 offset:16 scope:SCOPE_SE
146+
; GCN-SDAG-NEXT: ; meta instruction
181147
; GCN-SDAG-NEXT: scratch_store_b32 off, v60, s32 offset:12 scope:SCOPE_SE
148+
; GCN-SDAG-NEXT: ; meta instruction
182149
; GCN-SDAG-NEXT: scratch_store_b32 off, v61, s32 offset:8 scope:SCOPE_SE
150+
; GCN-SDAG-NEXT: ; meta instruction
183151
; GCN-SDAG-NEXT: scratch_store_b32 off, v62, s32 offset:4 scope:SCOPE_SE
152+
; GCN-SDAG-NEXT: ; meta instruction
184153
; GCN-SDAG-NEXT: scratch_store_b32 off, v63, s32 scope:SCOPE_SE
185-
>>>>>>> 5f20518f5b4734d01848dfe44d24aed195dc2043
186154
; GCN-SDAG-NEXT: global_load_b128 v[6:9], v[0:1], off offset:224
187155
; GCN-SDAG-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v3
188156
; GCN-SDAG-NEXT: s_wait_loadcnt 0x0
@@ -251,73 +219,37 @@ define i32 @test_v64i32_load_store(ptr addrspace(1) %ptr, i32 %idx, ptr addrspac
251219
; GCN-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
252220
; GCN-GISEL-NEXT: s_wait_kmcnt 0x0
253221
; GCN-GISEL-NEXT: s_clause 0xf
254-
<<<<<<< HEAD
255-
; GCN-GISEL-NEXT: scratch_store_b32 off, v40, s32 offset:60
256-
; GCN-GISEL-NEXT: ; meta instruction
257-
; GCN-GISEL-NEXT: scratch_store_b32 off, v41, s32 offset:56
258-
; GCN-GISEL-NEXT: ; meta instruction
259-
; GCN-GISEL-NEXT: scratch_store_b32 off, v42, s32 offset:52
260-
; GCN-GISEL-NEXT: ; meta instruction
261-
; GCN-GISEL-NEXT: scratch_store_b32 off, v43, s32 offset:48
262-
; GCN-GISEL-NEXT: ; meta instruction
263-
; GCN-GISEL-NEXT: scratch_store_b32 off, v44, s32 offset:44
264-
; GCN-GISEL-NEXT: ; meta instruction
265-
; GCN-GISEL-NEXT: scratch_store_b32 off, v45, s32 offset:40
266-
; GCN-GISEL-NEXT: ; meta instruction
267-
; GCN-GISEL-NEXT: scratch_store_b32 off, v46, s32 offset:36
268-
; GCN-GISEL-NEXT: ; meta instruction
269-
; GCN-GISEL-NEXT: scratch_store_b32 off, v47, s32 offset:32
270-
; GCN-GISEL-NEXT: ; meta instruction
271-
; GCN-GISEL-NEXT: scratch_store_b32 off, v56, s32 offset:28
272-
; GCN-GISEL-NEXT: ; meta instruction
273-
; GCN-GISEL-NEXT: scratch_store_b32 off, v57, s32 offset:24
274-
; GCN-GISEL-NEXT: ; meta instruction
275-
; GCN-GISEL-NEXT: scratch_store_b32 off, v58, s32 offset:20
276-
; GCN-GISEL-NEXT: ; meta instruction
277-
; GCN-GISEL-NEXT: scratch_store_b32 off, v59, s32 offset:16
278-
; GCN-GISEL-NEXT: ; meta instruction
279-
; GCN-GISEL-NEXT: scratch_store_b32 off, v60, s32 offset:12
280-
; GCN-GISEL-NEXT: ; meta instruction
281-
; GCN-GISEL-NEXT: scratch_store_b32 off, v61, s32 offset:8
282-
; GCN-GISEL-NEXT: ; meta instruction
283-
; GCN-GISEL-NEXT: scratch_store_b32 off, v62, s32 offset:4
284-
; GCN-GISEL-NEXT: ; meta instruction
285-
; GCN-GISEL-NEXT: scratch_store_b32 off, v63, s32
286-
||||||| 5050a1507116
287-
; GCN-GISEL-NEXT: scratch_store_b32 off, v40, s32 offset:60
288-
; GCN-GISEL-NEXT: scratch_store_b32 off, v41, s32 offset:56
289-
; GCN-GISEL-NEXT: scratch_store_b32 off, v42, s32 offset:52
290-
; GCN-GISEL-NEXT: scratch_store_b32 off, v43, s32 offset:48
291-
; GCN-GISEL-NEXT: scratch_store_b32 off, v44, s32 offset:44
292-
; GCN-GISEL-NEXT: scratch_store_b32 off, v45, s32 offset:40
293-
; GCN-GISEL-NEXT: scratch_store_b32 off, v46, s32 offset:36
294-
; GCN-GISEL-NEXT: scratch_store_b32 off, v47, s32 offset:32
295-
; GCN-GISEL-NEXT: scratch_store_b32 off, v56, s32 offset:28
296-
; GCN-GISEL-NEXT: scratch_store_b32 off, v57, s32 offset:24
297-
; GCN-GISEL-NEXT: scratch_store_b32 off, v58, s32 offset:20
298-
; GCN-GISEL-NEXT: scratch_store_b32 off, v59, s32 offset:16
299-
; GCN-GISEL-NEXT: scratch_store_b32 off, v60, s32 offset:12
300-
; GCN-GISEL-NEXT: scratch_store_b32 off, v61, s32 offset:8
301-
; GCN-GISEL-NEXT: scratch_store_b32 off, v62, s32 offset:4
302-
; GCN-GISEL-NEXT: scratch_store_b32 off, v63, s32
303-
=======
304222
; GCN-GISEL-NEXT: scratch_store_b32 off, v40, s32 offset:60 scope:SCOPE_SE
223+
; GCN-GISEL-NEXT: ; meta instruction
305224
; GCN-GISEL-NEXT: scratch_store_b32 off, v41, s32 offset:56 scope:SCOPE_SE
225+
; GCN-GISEL-NEXT: ; meta instruction
306226
; GCN-GISEL-NEXT: scratch_store_b32 off, v42, s32 offset:52 scope:SCOPE_SE
227+
; GCN-GISEL-NEXT: ; meta instruction
307228
; GCN-GISEL-NEXT: scratch_store_b32 off, v43, s32 offset:48 scope:SCOPE_SE
229+
; GCN-GISEL-NEXT: ; meta instruction
308230
; GCN-GISEL-NEXT: scratch_store_b32 off, v44, s32 offset:44 scope:SCOPE_SE
231+
; GCN-GISEL-NEXT: ; meta instruction
309232
; GCN-GISEL-NEXT: scratch_store_b32 off, v45, s32 offset:40 scope:SCOPE_SE
233+
; GCN-GISEL-NEXT: ; meta instruction
310234
; GCN-GISEL-NEXT: scratch_store_b32 off, v46, s32 offset:36 scope:SCOPE_SE
235+
; GCN-GISEL-NEXT: ; meta instruction
311236
; GCN-GISEL-NEXT: scratch_store_b32 off, v47, s32 offset:32 scope:SCOPE_SE
237+
; GCN-GISEL-NEXT: ; meta instruction
312238
; GCN-GISEL-NEXT: scratch_store_b32 off, v56, s32 offset:28 scope:SCOPE_SE
239+
; GCN-GISEL-NEXT: ; meta instruction
313240
; GCN-GISEL-NEXT: scratch_store_b32 off, v57, s32 offset:24 scope:SCOPE_SE
241+
; GCN-GISEL-NEXT: ; meta instruction
314242
; GCN-GISEL-NEXT: scratch_store_b32 off, v58, s32 offset:20 scope:SCOPE_SE
243+
; GCN-GISEL-NEXT: ; meta instruction
315244
; GCN-GISEL-NEXT: scratch_store_b32 off, v59, s32 offset:16 scope:SCOPE_SE
245+
; GCN-GISEL-NEXT: ; meta instruction
316246
; GCN-GISEL-NEXT: scratch_store_b32 off, v60, s32 offset:12 scope:SCOPE_SE
247+
; GCN-GISEL-NEXT: ; meta instruction
317248
; GCN-GISEL-NEXT: scratch_store_b32 off, v61, s32 offset:8 scope:SCOPE_SE
249+
; GCN-GISEL-NEXT: ; meta instruction
318250
; GCN-GISEL-NEXT: scratch_store_b32 off, v62, s32 offset:4 scope:SCOPE_SE
251+
; GCN-GISEL-NEXT: ; meta instruction
319252
; GCN-GISEL-NEXT: scratch_store_b32 off, v63, s32 scope:SCOPE_SE
320-
>>>>>>> 5f20518f5b4734d01848dfe44d24aed195dc2043
321253
; GCN-GISEL-NEXT: s_wait_xcnt 0x8
322254
; GCN-GISEL-NEXT: v_dual_mov_b32 v46, v3 :: v_dual_mov_b32 v47, v4
323255
; GCN-GISEL-NEXT: global_load_b128 v[2:5], v[0:1], off offset:32
@@ -395,25 +327,13 @@ define i64 @test_v16i64_load_store(ptr addrspace(1) %ptr_a, ptr addrspace(1) %pt
395327
; GCN-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
396328
; GCN-SDAG-NEXT: s_wait_kmcnt 0x0
397329
; GCN-SDAG-NEXT: s_clause 0x3
398-
<<<<<<< HEAD
399-
; GCN-SDAG-NEXT: scratch_store_b32 off, v40, s32 offset:12
400-
; GCN-SDAG-NEXT: ; meta instruction
401-
; GCN-SDAG-NEXT: scratch_store_b32 off, v41, s32 offset:8
402-
; GCN-SDAG-NEXT: ; meta instruction
403-
; GCN-SDAG-NEXT: scratch_store_b32 off, v42, s32 offset:4
404-
; GCN-SDAG-NEXT: ; meta instruction
405-
; GCN-SDAG-NEXT: scratch_store_b32 off, v43, s32
406-
||||||| 5050a1507116
407-
; GCN-SDAG-NEXT: scratch_store_b32 off, v40, s32 offset:12
408-
; GCN-SDAG-NEXT: scratch_store_b32 off, v41, s32 offset:8
409-
; GCN-SDAG-NEXT: scratch_store_b32 off, v42, s32 offset:4
410-
; GCN-SDAG-NEXT: scratch_store_b32 off, v43, s32
411-
=======
412330
; GCN-SDAG-NEXT: scratch_store_b32 off, v40, s32 offset:12 scope:SCOPE_SE
331+
; GCN-SDAG-NEXT: ; meta instruction
413332
; GCN-SDAG-NEXT: scratch_store_b32 off, v41, s32 offset:8 scope:SCOPE_SE
333+
; GCN-SDAG-NEXT: ; meta instruction
414334
; GCN-SDAG-NEXT: scratch_store_b32 off, v42, s32 offset:4 scope:SCOPE_SE
335+
; GCN-SDAG-NEXT: ; meta instruction
415336
; GCN-SDAG-NEXT: scratch_store_b32 off, v43, s32 scope:SCOPE_SE
416-
>>>>>>> 5f20518f5b4734d01848dfe44d24aed195dc2043
417337
; GCN-SDAG-NEXT: s_clause 0x7
418338
; GCN-SDAG-NEXT: global_load_b128 v[10:13], v[0:1], off offset:112
419339
; GCN-SDAG-NEXT: global_load_b128 v[18:21], v[0:1], off offset:96
@@ -496,33 +416,17 @@ define i64 @test_v16i64_load_store(ptr addrspace(1) %ptr_a, ptr addrspace(1) %pt
496416
; GCN-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
497417
; GCN-GISEL-NEXT: s_wait_kmcnt 0x0
498418
; GCN-GISEL-NEXT: s_clause 0x5
499-
<<<<<<< HEAD
500-
; GCN-GISEL-NEXT: scratch_store_b32 off, v40, s32 offset:20
501-
; GCN-GISEL-NEXT: ; meta instruction
502-
; GCN-GISEL-NEXT: scratch_store_b32 off, v41, s32 offset:16
503-
; GCN-GISEL-NEXT: ; meta instruction
504-
; GCN-GISEL-NEXT: scratch_store_b32 off, v42, s32 offset:12
505-
; GCN-GISEL-NEXT: ; meta instruction
506-
; GCN-GISEL-NEXT: scratch_store_b32 off, v43, s32 offset:8
507-
; GCN-GISEL-NEXT: ; meta instruction
508-
; GCN-GISEL-NEXT: scratch_store_b32 off, v44, s32 offset:4
509-
; GCN-GISEL-NEXT: ; meta instruction
510-
; GCN-GISEL-NEXT: scratch_store_b32 off, v45, s32
511-
||||||| 5050a1507116
512-
; GCN-GISEL-NEXT: scratch_store_b32 off, v40, s32 offset:20
513-
; GCN-GISEL-NEXT: scratch_store_b32 off, v41, s32 offset:16
514-
; GCN-GISEL-NEXT: scratch_store_b32 off, v42, s32 offset:12
515-
; GCN-GISEL-NEXT: scratch_store_b32 off, v43, s32 offset:8
516-
; GCN-GISEL-NEXT: scratch_store_b32 off, v44, s32 offset:4
517-
; GCN-GISEL-NEXT: scratch_store_b32 off, v45, s32
518-
=======
519419
; GCN-GISEL-NEXT: scratch_store_b32 off, v40, s32 offset:20 scope:SCOPE_SE
420+
; GCN-GISEL-NEXT: ; meta instruction
520421
; GCN-GISEL-NEXT: scratch_store_b32 off, v41, s32 offset:16 scope:SCOPE_SE
422+
; GCN-GISEL-NEXT: ; meta instruction
521423
; GCN-GISEL-NEXT: scratch_store_b32 off, v42, s32 offset:12 scope:SCOPE_SE
424+
; GCN-GISEL-NEXT: ; meta instruction
522425
; GCN-GISEL-NEXT: scratch_store_b32 off, v43, s32 offset:8 scope:SCOPE_SE
426+
; GCN-GISEL-NEXT: ; meta instruction
523427
; GCN-GISEL-NEXT: scratch_store_b32 off, v44, s32 offset:4 scope:SCOPE_SE
428+
; GCN-GISEL-NEXT: ; meta instruction
524429
; GCN-GISEL-NEXT: scratch_store_b32 off, v45, s32 scope:SCOPE_SE
525-
>>>>>>> 5f20518f5b4734d01848dfe44d24aed195dc2043
526430
; GCN-GISEL-NEXT: s_clause 0x7
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; GCN-GISEL-NEXT: global_load_b128 v[6:9], v[0:1], off offset:80
528432
; GCN-GISEL-NEXT: global_load_b128 v[10:13], v[0:1], off

‎llvm/test/CodeGen/AMDGPU/partial-regcopy-and-spill-missed-at-regalloc.ll‎

Lines changed: 0 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -81,18 +81,8 @@ define amdgpu_kernel void @partial_copy(<4 x i32> %arg) #0 {
8181
; PEI-GFX90A: bb.0 (%ir-block.0):
8282
; PEI-GFX90A-NEXT: liveins: $sgpr4_sgpr5
8383
; PEI-GFX90A-NEXT: {{ $}}
84-
<<<<<<< HEAD
8584
; PEI-GFX90A-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02
8685
; PEI-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg
87-
; PEI-GFX90A-NEXT: $sgpr12_sgpr13_sgpr14_sgpr15 = COPY killed $sgpr0_sgpr1_sgpr2_sgpr3
88-
; PEI-GFX90A-NEXT: $sgpr12 = S_ADD_U32 $sgpr12, $sgpr9, implicit-def $scc, implicit-def $sgpr12_sgpr13_sgpr14_sgpr15
89-
; PEI-GFX90A-NEXT: $sgpr13 = S_ADDC_U32 $sgpr13, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr12_sgpr13_sgpr14_sgpr15
90-
||||||| 5050a1507116
91-
; PEI-GFX90A-NEXT: $sgpr12_sgpr13_sgpr14_sgpr15 = COPY killed $sgpr0_sgpr1_sgpr2_sgpr3
92-
; PEI-GFX90A-NEXT: $sgpr12 = S_ADD_U32 $sgpr12, $sgpr9, implicit-def $scc, implicit-def $sgpr12_sgpr13_sgpr14_sgpr15
93-
; PEI-GFX90A-NEXT: $sgpr13 = S_ADDC_U32 $sgpr13, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr12_sgpr13_sgpr14_sgpr15
94-
=======
95-
>>>>>>> 5f20518f5b4734d01848dfe44d24aed195dc2043
9686
; PEI-GFX90A-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2162697 /* reguse:AGPR_32 */, undef renamable $agpr0
9787
; PEI-GFX90A-NEXT: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 6422538 /* regdef:VReg_128_Align2 */, def renamable $vgpr0_vgpr1_vgpr2_vgpr3
9888
; PEI-GFX90A-NEXT: renamable $agpr0_agpr1_agpr2_agpr3 = COPY killed renamable $vgpr0_vgpr1_vgpr2_vgpr3, implicit $exec

‎llvm/test/CodeGen/AMDGPU/post-ra-soft-clause-dbg-info.ll‎

Lines changed: 1 addition & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -1,11 +1,4 @@
1-
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2-
<<<<<<< HEAD
3-
; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -mattr=+xnack -amdgpu-max-memory-clause=0 -experimental-debug-variable-locations=false -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN %s
4-
||||||| 5050a1507116
5-
; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -mattr=+xnack -amdgpu-max-memory-clause=0 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN %s
6-
=======
7-
; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -mattr=+xnack -amdgpu-max-memory-clause=0 < %s | FileCheck -enable-var-scope -check-prefix=GCN %s
8-
>>>>>>> 5f20518f5b4734d01848dfe44d24aed195dc2043
1+
; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -mattr=+xnack -amdgpu-max-memory-clause=0 -experimental-debug-variable-locations=false < %s | FileCheck -enable-var-scope -check-prefix=GCN %s
92

103
; Test the behavior of the post-RA soft clause bundler in the presence
114
; of debug info. The debug info should not interfere with the

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