@@ -1326,14 +1326,14 @@ class Base_DS_Real_gfx6_gfx7_gfx10_gfx11_gfx12<bits<8> op, DS_Pseudo ps, int ef,
13261326// GFX12.
13271327//===----------------------------------------------------------------------===//
13281328
1329- multiclass DS_Real_gfx12<bits<8> op, string name = !tolower(NAME), bit needAlias = true > {
1329+ multiclass DS_Real_gfx12<bits<8> op, string name = !tolower(NAME)> {
13301330 defvar ps = !cast<DS_Pseudo>(NAME);
13311331 let AssemblerPredicate = isGFX12Plus in {
13321332 let DecoderNamespace = "GFX12" in
13331333 def _gfx12 :
13341334 Base_DS_Real_gfx6_gfx7_gfx10_gfx11_gfx12<op, ps, SIEncodingFamily.GFX12,
13351335 name, /*hasGDS=*/false>;
1336- if !and(needAlias, ! ne(ps.Mnemonic, name) ) then
1336+ if !ne(ps.Mnemonic, name) then
13371337 def : AMDGPUMnemonicAlias<ps.Mnemonic, name>;
13381338 } // End AssemblerPredicate
13391339}
@@ -1362,7 +1362,7 @@ defm DS_LOAD_TR16_B128 : DS_Real_gfx12<0x0fc>;
13621362defm DS_LOAD_TR8_B64 : DS_Real_gfx12<0x0fd>;
13631363
13641364defm DS_BVH_STACK_RTN_B32 : DS_Real_gfx12<0x0e0,
1365- "ds_bvh_stack_push4_pop1_rtn_b32", true >;
1365+ "ds_bvh_stack_push4_pop1_rtn_b32">;
13661366defm DS_BVH_STACK_PUSH8_POP1_RTN_B32 : DS_Real_gfx12<0x0e1>;
13671367defm DS_BVH_STACK_PUSH8_POP2_RTN_B64 : DS_Real_gfx12<0x0e2>;
13681368
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