[AArch64] Have isel just do neg directly

This means we do not have to rely on register coalescing to fix this, which matches gcc outputting things like neg on -O0

Author: AZero13

llvm/lib/Target/AArch64/AArch64FastISel.cpp

@@ -1201,6 +1201,19 @@ Register AArch64FastISel::emitAddSub(bool UseAdd, MVT RetVT, const Value *LHS,
             SI->getOpcode() == Instruction::AShr   )
           std::swap(LHS, RHS);
 
+  // Special case: sub 0, x -> neg x (use zero register directly)
+  if (!UseAdd && isa<Constant>(LHS) && cast<Constant>(LHS)->isNullValue()) {
+    Register RHSReg = getRegForValue(RHS);
+    if (!RHSReg)
+      return Register();
+
+    if (NeedExtend)
+      RHSReg = emitIntExt(SrcVT, RHSReg, RetVT, IsZExt);
+
+    Register ZeroReg = RetVT == MVT::i64 ? AArch64::XZR : AArch64::WZR;
+    return emitAddSub_rr(UseAdd, RetVT, ZeroReg, RHSReg, SetFlags, WantResult);
+  }
+
   Register LHSReg = getRegForValue(LHS);
   if (!LHSReg)
     return Register();

llvm/test/CodeGen/AArch64/instruct-neg.ll

@@ -4,8 +4,7 @@
 define i32 @negb(i32 %b) {
 ; CHECK-LABEL: negb:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, wzr
-; CHECK-NEXT:    sub w0, w8, w0
+; CHECK-NEXT:    neg w0, w0
 ; CHECK-NEXT:    ret
   %sub = sub nsw i32 0, %b
   ret i32 %sub