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mattarde
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update comef opt on 10_2
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‎llvm/lib/Target/X86/X86ISelLowering.cpp‎

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -49520,6 +49520,15 @@ static SDValue combineCompareEqual(SDNode *N, SelectionDAG &DAG,
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// FIXME: need symbolic constants for these magic numbers.
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// See X86ATTInstPrinter.cpp:printSSECC().
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unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
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// VCOMXSS simplifies conditional code sequence into single setcc node
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// and a CC node, Earlier until COMI, it required 2 SETCC's
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if (Subtarget.hasAVX10_2()) {
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return getSETCC(
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((cc0 == X86::COND_E) ? X86::COND_E : X86::COND_NE),
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DAG.getNode(X86ISD::UCOMX, DL, MVT::i32, CMP00, CMP01), DL,
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DAG);
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}
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if (Subtarget.hasAVX512()) {
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SDValue FSetCC =
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DAG.getNode(X86ISD::FSETCCM, DL, MVT::v1i1, CMP00, CMP01,

‎llvm/lib/Target/X86/X86InstrAVX10.td‎

Lines changed: 23 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1541,6 +1541,24 @@ defm VFNMSUB132NEPBF16 : avx10_fma3p_132_bf16<0x9E, "vfnmsub132nepbf16", X86any_
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//-------------------------------------------------
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// AVX10 COMEF instructions
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//-------------------------------------------------
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multiclass avx10_com_ef<bits<8> Opc, RegisterClass RC, ValueType VT,
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SDPatternOperator OpNode, string OpcodeStr,
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X86MemOperand x86memop, PatFrag ld_frag,
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Domain d, X86FoldableSchedWrite sched = WriteFComX>{
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let ExeDomain = d, mayRaiseFPException = 1, isCodeGenOnly = 1 in {
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def rr : AVX512<Opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
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[(set EFLAGS, (OpNode (VT RC:$src1), RC:$src2))]>,
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EVEX, EVEX_V128, Sched<[sched]>, SIMD_EXC;
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let mayLoad = 1 in {
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def rm : AVX512<Opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
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[(set EFLAGS, (OpNode (VT RC:$src1), (ld_frag addr:$src2)))]>,
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EVEX, EVEX_V128, Sched<[sched.Folded, sched.ReadAfterFold]>, SIMD_EXC;
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}
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}
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}
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multiclass avx10_com_ef_int<bits<8> Opc, X86VectorVTInfo _, SDNode OpNode,
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string OpcodeStr,
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Domain d,
@@ -1564,6 +1582,11 @@ multiclass avx10_com_ef_int<bits<8> Opc, X86VectorVTInfo _, SDNode OpNode,
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}
15651583

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let Defs = [EFLAGS], Uses = [MXCSR], Predicates = [HasAVX10_2] in {
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defm VUCOMXSSZ : avx10_com_ef<0x2e, FR32X, f32, X86ucomi512,
1587+
"vucomxss", f32mem, loadf32, SSEPackedSingle>,
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TB, XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
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defm VCOMXSDZ : avx10_com_ef_int<0x2f, v2f64x_info, X86comi512,
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"vcomxsd", SSEPackedDouble>,
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TB, XS, VEX_LIG, REX_W, EVEX_CD8<64, CD8VT1>;

‎llvm/test/CodeGen/X86/avx10_2-cmp.ll‎

Lines changed: 121 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,121 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
2+
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx10.2-512 | FileCheck %s --check-prefix=AVX10_2_X64
3+
; RUN: llc < %s -mtriple=i386-unknown-unknown -mattr=+avx10.2-512 | FileCheck %s --check-prefix=AVX10_2_X86
4+
5+
define i1 @oeq(float %x, float %y) {
6+
; AVX10_2_X64-LABEL: oeq:
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; AVX10_2_X64: # %bb.0:
8+
; AVX10_2_X64-NEXT: vucomxss %xmm1, %xmm0
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; AVX10_2_X64-NEXT: sete %al
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; AVX10_2_X64-NEXT: retq
11+
;
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; AVX10_2_X86-LABEL: oeq:
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; AVX10_2_X86: # %bb.0:
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; AVX10_2_X86-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
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; AVX10_2_X86-NEXT: vucomxss {{[0-9]+}}(%esp), %xmm0
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; AVX10_2_X86-NEXT: sete %al
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; AVX10_2_X86-NEXT: retl
18+
%1 = fcmp oeq float %x, %y
19+
ret i1 %1
20+
}
21+
22+
define i1 @une(float %x, float %y) {
23+
; AVX10_2_X64-LABEL: une:
24+
; AVX10_2_X64: # %bb.0:
25+
; AVX10_2_X64-NEXT: vucomxss %xmm1, %xmm0
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; AVX10_2_X64-NEXT: setne %al
27+
; AVX10_2_X64-NEXT: retq
28+
;
29+
; AVX10_2_X86-LABEL: une:
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; AVX10_2_X86: # %bb.0:
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; AVX10_2_X86-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
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; AVX10_2_X86-NEXT: vucomxss {{[0-9]+}}(%esp), %xmm0
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; AVX10_2_X86-NEXT: setne %al
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; AVX10_2_X86-NEXT: retl
35+
%1 = fcmp une float %x, %y
36+
ret i1 %1
37+
}
38+
39+
define i1 @ogt(float %x, float %y) {
40+
; AVX10_2_X64-LABEL: ogt:
41+
; AVX10_2_X64: # %bb.0:
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; AVX10_2_X64-NEXT: vucomiss %xmm1, %xmm0
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; AVX10_2_X64-NEXT: seta %al
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; AVX10_2_X64-NEXT: retq
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;
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; AVX10_2_X86-LABEL: ogt:
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; AVX10_2_X86: # %bb.0:
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; AVX10_2_X86-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
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; AVX10_2_X86-NEXT: vucomiss {{[0-9]+}}(%esp), %xmm0
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; AVX10_2_X86-NEXT: seta %al
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; AVX10_2_X86-NEXT: retl
52+
%1 = fcmp ogt float %x, %y
53+
ret i1 %1
54+
}
55+
56+
define i1 @oeq_mem(ptr %xp, ptr %yp) {
57+
; AVX10_2_X64-LABEL: oeq_mem:
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; AVX10_2_X64: # %bb.0:
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; AVX10_2_X64-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
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; AVX10_2_X64-NEXT: vucomxss (%rsi), %xmm0
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; AVX10_2_X64-NEXT: sete %al
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; AVX10_2_X64-NEXT: retq
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;
64+
; AVX10_2_X86-LABEL: oeq_mem:
65+
; AVX10_2_X86: # %bb.0:
66+
; AVX10_2_X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; AVX10_2_X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
68+
; AVX10_2_X86-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
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; AVX10_2_X86-NEXT: vucomxss (%eax), %xmm0
70+
; AVX10_2_X86-NEXT: sete %al
71+
; AVX10_2_X86-NEXT: retl
72+
%x = load float, ptr %xp
73+
%y = load float, ptr %yp
74+
%1 = fcmp oeq float %x, %y
75+
ret i1 %1
76+
}
77+
78+
define i1 @une_mem(ptr %xp, ptr %yp) {
79+
; AVX10_2_X64-LABEL: une_mem:
80+
; AVX10_2_X64: # %bb.0:
81+
; AVX10_2_X64-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
82+
; AVX10_2_X64-NEXT: vucomxss (%rsi), %xmm0
83+
; AVX10_2_X64-NEXT: setne %al
84+
; AVX10_2_X64-NEXT: retq
85+
;
86+
; AVX10_2_X86-LABEL: une_mem:
87+
; AVX10_2_X86: # %bb.0:
88+
; AVX10_2_X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; AVX10_2_X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; AVX10_2_X86-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
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; AVX10_2_X86-NEXT: vucomxss (%eax), %xmm0
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; AVX10_2_X86-NEXT: setne %al
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; AVX10_2_X86-NEXT: retl
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%x = load float, ptr %xp
95+
%y = load float, ptr %yp
96+
%1 = fcmp une float %x, %y
97+
ret i1 %1
98+
}
99+
100+
101+
define i1 @ogt_mem(ptr %xp, ptr %yp) {
102+
; AVX10_2_X64-LABEL: ogt_mem:
103+
; AVX10_2_X64: # %bb.0:
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; AVX10_2_X64-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
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; AVX10_2_X64-NEXT: vucomiss (%rsi), %xmm0
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; AVX10_2_X64-NEXT: seta %al
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; AVX10_2_X64-NEXT: retq
108+
;
109+
; AVX10_2_X86-LABEL: ogt_mem:
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; AVX10_2_X86: # %bb.0:
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; AVX10_2_X86-NEXT: movl {{[0-9]+}}(%esp), %eax
112+
; AVX10_2_X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; AVX10_2_X86-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
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; AVX10_2_X86-NEXT: vucomiss (%eax), %xmm0
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; AVX10_2_X86-NEXT: seta %al
116+
; AVX10_2_X86-NEXT: retl
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%x = load float, ptr %xp
118+
%y = load float, ptr %yp
119+
%1 = fcmp ogt float %x, %y
120+
ret i1 %1
121+
}

‎llvm/test/TableGen/x86-fold-tables.inc‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1961,6 +1961,7 @@ static const X86FoldTableEntry Table1[] = {
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{X86::VUCOMISSrr_Int, X86::VUCOMISSrm_Int, TB_NO_REVERSE},
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{X86::VUCOMXSDZrr_Int, X86::VUCOMXSDZrm_Int, TB_NO_REVERSE},
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{X86::VUCOMXSHZrr_Int, X86::VUCOMXSHZrm_Int, TB_NO_REVERSE},
1964+
{X86::VUCOMXSSZrr, X86::VUCOMXSSZrm, 0},
19641965
{X86::VUCOMXSSZrr_Int, X86::VUCOMXSSZrm_Int, TB_NO_REVERSE},
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{X86::XOR16ri8_ND, X86::XOR16mi8_ND, 0},
19661967
{X86::XOR16ri8_NF_ND, X86::XOR16mi8_NF_ND, 0},

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