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Rename out-of-range tests. Remove bogus constant predicates.
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‎llvm/test/CodeGen/AArch64/sve2-intrinsics-uniform-dsp-undef.ll‎

Lines changed: 32 additions & 48 deletions
Original file line numberDiff line numberDiff line change
@@ -345,8 +345,8 @@ define <vscale x 2 x i64> @sqshl_n_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64>
345345
ret <vscale x 2 x i64> %out
346346
}
347347

348-
define <vscale x 16 x i8> @sqshl_n_i8_range(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a) {
349-
; CHECK-LABEL: sqshl_n_i8_range:
348+
define <vscale x 16 x i8> @sqshl_n_i8_out_of_range(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a) {
349+
; CHECK-LABEL: sqshl_n_i8_out_of_range:
350350
; CHECK: // %bb.0:
351351
; CHECK-NEXT: mov z1.b, #8 // =0x8
352352
; CHECK-NEXT: sqshl z0.b, p0/m, z0.b, z1.b
@@ -357,8 +357,8 @@ define <vscale x 16 x i8> @sqshl_n_i8_range(<vscale x 16 x i1> %pg, <vscale x 16
357357
ret <vscale x 16 x i8> %out
358358
}
359359

360-
define <vscale x 8 x i16> @sqshl_n_i16_range(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a) {
361-
; CHECK-LABEL: sqshl_n_i16_range:
360+
define <vscale x 8 x i16> @sqshl_n_i16_out_of_range(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a) {
361+
; CHECK-LABEL: sqshl_n_i16_out_of_range:
362362
; CHECK: // %bb.0:
363363
; CHECK-NEXT: mov z1.h, #16 // =0x10
364364
; CHECK-NEXT: sqshl z0.h, p0/m, z0.h, z1.h
@@ -369,8 +369,8 @@ define <vscale x 8 x i16> @sqshl_n_i16_range(<vscale x 8 x i1> %pg, <vscale x 8
369369
ret <vscale x 8 x i16> %out
370370
}
371371

372-
define <vscale x 4 x i32> @sqshl_n_i32_range(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) {
373-
; CHECK-LABEL: sqshl_n_i32_range:
372+
define <vscale x 4 x i32> @sqshl_n_i32_out_of_range(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) {
373+
; CHECK-LABEL: sqshl_n_i32_out_of_range:
374374
; CHECK: // %bb.0:
375375
; CHECK-NEXT: mov z1.s, #32 // =0x20
376376
; CHECK-NEXT: sqshl z0.s, p0/m, z0.s, z1.s
@@ -381,8 +381,8 @@ define <vscale x 4 x i32> @sqshl_n_i32_range(<vscale x 4 x i1> %pg, <vscale x 4
381381
ret <vscale x 4 x i32> %out
382382
}
383383

384-
define <vscale x 2 x i64> @sqshl_n_i64_range(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a) {
385-
; CHECK-LABEL: sqshl_n_i64_range:
384+
define <vscale x 2 x i64> @sqshl_n_i64_out_of_range(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a) {
385+
; CHECK-LABEL: sqshl_n_i64_out_of_range:
386386
; CHECK: // %bb.0:
387387
; CHECK-NEXT: mov z1.d, #64 // =0x40
388388
; CHECK-NEXT: sqshl z0.d, p0/m, z0.d, z1.d
@@ -548,10 +548,9 @@ define <vscale x 2 x i64> @srshl_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %
548548
define <vscale x 16 x i8> @srshl_i8_swapped_operands(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
549549
; CHECK-LABEL: srshl_i8_swapped_operands:
550550
; CHECK: // %bb.0:
551-
; CHECK-NEXT: ptrue p0.b
552551
; CHECK-NEXT: srshlr z0.b, p0/m, z0.b, z1.b
553552
; CHECK-NEXT: ret
554-
%out = call <vscale x 16 x i8> @llvm.aarch64.sve.srshl.u.nxv16i8(<vscale x 16 x i1> splat(i1 true),
553+
%out = call <vscale x 16 x i8> @llvm.aarch64.sve.srshl.u.nxv16i8(<vscale x 16 x i1> %pg,
555554
<vscale x 16 x i8> %b,
556555
<vscale x 16 x i8> %a)
557556
ret <vscale x 16 x i8> %out
@@ -560,10 +559,9 @@ define <vscale x 16 x i8> @srshl_i8_swapped_operands(<vscale x 16 x i1> %pg, <vs
560559
define <vscale x 8 x i16> @srshl_i16_swapped_operands(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
561560
; CHECK-LABEL: srshl_i16_swapped_operands:
562561
; CHECK: // %bb.0:
563-
; CHECK-NEXT: ptrue p0.h
564562
; CHECK-NEXT: srshlr z0.h, p0/m, z0.h, z1.h
565563
; CHECK-NEXT: ret
566-
%out = call <vscale x 8 x i16> @llvm.aarch64.sve.srshl.u.nxv8i16(<vscale x 8 x i1> splat(i1 true),
564+
%out = call <vscale x 8 x i16> @llvm.aarch64.sve.srshl.u.nxv8i16(<vscale x 8 x i1> %pg,
567565
<vscale x 8 x i16> %b,
568566
<vscale x 8 x i16> %a)
569567
ret <vscale x 8 x i16> %out
@@ -572,10 +570,9 @@ define <vscale x 8 x i16> @srshl_i16_swapped_operands(<vscale x 8 x i1> %pg, <vs
572570
define <vscale x 4 x i32> @srshl_i32_swapped_operands(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
573571
; CHECK-LABEL: srshl_i32_swapped_operands:
574572
; CHECK: // %bb.0:
575-
; CHECK-NEXT: ptrue p0.s
576573
; CHECK-NEXT: srshlr z0.s, p0/m, z0.s, z1.s
577574
; CHECK-NEXT: ret
578-
%out = call <vscale x 4 x i32> @llvm.aarch64.sve.srshl.u.nxv4i32(<vscale x 4 x i1> splat(i1 true),
575+
%out = call <vscale x 4 x i32> @llvm.aarch64.sve.srshl.u.nxv4i32(<vscale x 4 x i1> %pg,
579576
<vscale x 4 x i32> %b,
580577
<vscale x 4 x i32> %a)
581578
ret <vscale x 4 x i32> %out
@@ -584,10 +581,9 @@ define <vscale x 4 x i32> @srshl_i32_swapped_operands(<vscale x 4 x i1> %pg, <vs
584581
define <vscale x 2 x i64> @srshl_i64_swapped_operands(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
585582
; CHECK-LABEL: srshl_i64_swapped_operands:
586583
; CHECK: // %bb.0:
587-
; CHECK-NEXT: ptrue p0.d
588584
; CHECK-NEXT: srshlr z0.d, p0/m, z0.d, z1.d
589585
; CHECK-NEXT: ret
590-
%out = call <vscale x 2 x i64> @llvm.aarch64.sve.srshl.u.nxv2i64(<vscale x 2 x i1> splat(i1 true),
586+
%out = call <vscale x 2 x i64> @llvm.aarch64.sve.srshl.u.nxv2i64(<vscale x 2 x i1> %pg,
591587
<vscale x 2 x i64> %b,
592588
<vscale x 2 x i64> %a)
593589
ret <vscale x 2 x i64> %out
@@ -700,10 +696,9 @@ define <vscale x 2 x i64> @uqrshl_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64>
700696
define <vscale x 16 x i8> @uqrshl_i8_swapped_operands(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
701697
; CHECK-LABEL: uqrshl_i8_swapped_operands:
702698
; CHECK: // %bb.0:
703-
; CHECK-NEXT: ptrue p0.b
704699
; CHECK-NEXT: uqrshlr z0.b, p0/m, z0.b, z1.b
705700
; CHECK-NEXT: ret
706-
%out = call <vscale x 16 x i8> @llvm.aarch64.sve.uqrshl.u.nxv16i8(<vscale x 16 x i1> splat(i1 true),
701+
%out = call <vscale x 16 x i8> @llvm.aarch64.sve.uqrshl.u.nxv16i8(<vscale x 16 x i1> %pg,
707702
<vscale x 16 x i8> %b,
708703
<vscale x 16 x i8> %a)
709704
ret <vscale x 16 x i8> %out
@@ -712,10 +707,9 @@ define <vscale x 16 x i8> @uqrshl_i8_swapped_operands(<vscale x 16 x i1> %pg, <v
712707
define <vscale x 8 x i16> @uqrshl_i16_swapped_operands(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
713708
; CHECK-LABEL: uqrshl_i16_swapped_operands:
714709
; CHECK: // %bb.0:
715-
; CHECK-NEXT: ptrue p0.h
716710
; CHECK-NEXT: uqrshlr z0.h, p0/m, z0.h, z1.h
717711
; CHECK-NEXT: ret
718-
%out = call <vscale x 8 x i16> @llvm.aarch64.sve.uqrshl.u.nxv8i16(<vscale x 8 x i1> splat(i1 true),
712+
%out = call <vscale x 8 x i16> @llvm.aarch64.sve.uqrshl.u.nxv8i16(<vscale x 8 x i1> %pg,
719713
<vscale x 8 x i16> %b,
720714
<vscale x 8 x i16> %a)
721715
ret <vscale x 8 x i16> %out
@@ -724,10 +718,9 @@ define <vscale x 8 x i16> @uqrshl_i16_swapped_operands(<vscale x 8 x i1> %pg, <v
724718
define <vscale x 4 x i32> @uqrshl_i32_swapped_operands(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
725719
; CHECK-LABEL: uqrshl_i32_swapped_operands:
726720
; CHECK: // %bb.0:
727-
; CHECK-NEXT: ptrue p0.s
728721
; CHECK-NEXT: uqrshlr z0.s, p0/m, z0.s, z1.s
729722
; CHECK-NEXT: ret
730-
%out = call <vscale x 4 x i32> @llvm.aarch64.sve.uqrshl.u.nxv4i32(<vscale x 4 x i1> splat(i1 true),
723+
%out = call <vscale x 4 x i32> @llvm.aarch64.sve.uqrshl.u.nxv4i32(<vscale x 4 x i1> %pg,
731724
<vscale x 4 x i32> %b,
732725
<vscale x 4 x i32> %a)
733726
ret <vscale x 4 x i32> %out
@@ -736,10 +729,9 @@ define <vscale x 4 x i32> @uqrshl_i32_swapped_operands(<vscale x 4 x i1> %pg, <v
736729
define <vscale x 2 x i64> @uqrshl_i64_swapped_operands(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
737730
; CHECK-LABEL: uqrshl_i64_swapped_operands:
738731
; CHECK: // %bb.0:
739-
; CHECK-NEXT: ptrue p0.d
740732
; CHECK-NEXT: uqrshlr z0.d, p0/m, z0.d, z1.d
741733
; CHECK-NEXT: ret
742-
%out = call <vscale x 2 x i64> @llvm.aarch64.sve.uqrshl.u.nxv2i64(<vscale x 2 x i1> splat(i1 true),
734+
%out = call <vscale x 2 x i64> @llvm.aarch64.sve.uqrshl.u.nxv2i64(<vscale x 2 x i1> %pg,
743735
<vscale x 2 x i64> %b,
744736
<vscale x 2 x i64> %a)
745737
ret <vscale x 2 x i64> %out
@@ -852,10 +844,9 @@ define <vscale x 2 x i64> @uqshl_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %
852844
define <vscale x 16 x i8> @uqshl_i8_swapped_operands(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
853845
; CHECK-LABEL: uqshl_i8_swapped_operands:
854846
; CHECK: // %bb.0:
855-
; CHECK-NEXT: ptrue p0.b
856847
; CHECK-NEXT: uqshlr z0.b, p0/m, z0.b, z1.b
857848
; CHECK-NEXT: ret
858-
%out = call <vscale x 16 x i8> @llvm.aarch64.sve.uqshl.u.nxv16i8(<vscale x 16 x i1> splat(i1 true),
849+
%out = call <vscale x 16 x i8> @llvm.aarch64.sve.uqshl.u.nxv16i8(<vscale x 16 x i1> %pg,
859850
<vscale x 16 x i8> %b,
860851
<vscale x 16 x i8> %a)
861852
ret <vscale x 16 x i8> %out
@@ -864,10 +855,9 @@ define <vscale x 16 x i8> @uqshl_i8_swapped_operands(<vscale x 16 x i1> %pg, <vs
864855
define <vscale x 8 x i16> @uqshl_i16_swapped_operands(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
865856
; CHECK-LABEL: uqshl_i16_swapped_operands:
866857
; CHECK: // %bb.0:
867-
; CHECK-NEXT: ptrue p0.h
868858
; CHECK-NEXT: uqshlr z0.h, p0/m, z0.h, z1.h
869859
; CHECK-NEXT: ret
870-
%out = call <vscale x 8 x i16> @llvm.aarch64.sve.uqshl.u.nxv8i16(<vscale x 8 x i1> splat(i1 true),
860+
%out = call <vscale x 8 x i16> @llvm.aarch64.sve.uqshl.u.nxv8i16(<vscale x 8 x i1> %pg,
871861
<vscale x 8 x i16> %b,
872862
<vscale x 8 x i16> %a)
873863
ret <vscale x 8 x i16> %out
@@ -876,10 +866,9 @@ define <vscale x 8 x i16> @uqshl_i16_swapped_operands(<vscale x 8 x i1> %pg, <vs
876866
define <vscale x 4 x i32> @uqshl_i32_swapped_operands(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
877867
; CHECK-LABEL: uqshl_i32_swapped_operands:
878868
; CHECK: // %bb.0:
879-
; CHECK-NEXT: ptrue p0.s
880869
; CHECK-NEXT: uqshlr z0.s, p0/m, z0.s, z1.s
881870
; CHECK-NEXT: ret
882-
%out = call <vscale x 4 x i32> @llvm.aarch64.sve.uqshl.u.nxv4i32(<vscale x 4 x i1> splat(i1 true),
871+
%out = call <vscale x 4 x i32> @llvm.aarch64.sve.uqshl.u.nxv4i32(<vscale x 4 x i1> %pg,
883872
<vscale x 4 x i32> %b,
884873
<vscale x 4 x i32> %a)
885874
ret <vscale x 4 x i32> %out
@@ -888,10 +877,9 @@ define <vscale x 4 x i32> @uqshl_i32_swapped_operands(<vscale x 4 x i1> %pg, <vs
888877
define <vscale x 2 x i64> @uqshl_i64_swapped_operands(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
889878
; CHECK-LABEL: uqshl_i64_swapped_operands:
890879
; CHECK: // %bb.0:
891-
; CHECK-NEXT: ptrue p0.d
892880
; CHECK-NEXT: uqshlr z0.d, p0/m, z0.d, z1.d
893881
; CHECK-NEXT: ret
894-
%out = call <vscale x 2 x i64> @llvm.aarch64.sve.uqshl.u.nxv2i64(<vscale x 2 x i1> splat(i1 true),
882+
%out = call <vscale x 2 x i64> @llvm.aarch64.sve.uqshl.u.nxv2i64(<vscale x 2 x i1> %pg,
895883
<vscale x 2 x i64> %b,
896884
<vscale x 2 x i64> %a)
897885
ret <vscale x 2 x i64> %out
@@ -997,8 +985,8 @@ define <vscale x 2 x i64> @uqshl_n_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64>
997985
ret <vscale x 2 x i64> %out
998986
}
999987

1000-
define <vscale x 16 x i8> @uqshl_n_i8_range(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a) {
1001-
; CHECK-LABEL: uqshl_n_i8_range:
988+
define <vscale x 16 x i8> @uqshl_n_i8_out_of_range(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a) {
989+
; CHECK-LABEL: uqshl_n_i8_out_of_range:
1002990
; CHECK: // %bb.0:
1003991
; CHECK-NEXT: mov z1.b, #8 // =0x8
1004992
; CHECK-NEXT: uqshl z0.b, p0/m, z0.b, z1.b
@@ -1009,8 +997,8 @@ define <vscale x 16 x i8> @uqshl_n_i8_range(<vscale x 16 x i1> %pg, <vscale x 16
1009997
ret <vscale x 16 x i8> %out
1010998
}
1011999

1012-
define <vscale x 8 x i16> @uqshl_n_i16_range(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a) {
1013-
; CHECK-LABEL: uqshl_n_i16_range:
1000+
define <vscale x 8 x i16> @uqshl_n_i16_out_of_range(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a) {
1001+
; CHECK-LABEL: uqshl_n_i16_out_of_range:
10141002
; CHECK: // %bb.0:
10151003
; CHECK-NEXT: mov z1.h, #16 // =0x10
10161004
; CHECK-NEXT: uqshl z0.h, p0/m, z0.h, z1.h
@@ -1021,8 +1009,8 @@ define <vscale x 8 x i16> @uqshl_n_i16_range(<vscale x 8 x i1> %pg, <vscale x 8
10211009
ret <vscale x 8 x i16> %out
10221010
}
10231011

1024-
define <vscale x 4 x i32> @uqshl_n_i32_range(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) {
1025-
; CHECK-LABEL: uqshl_n_i32_range:
1012+
define <vscale x 4 x i32> @uqshl_n_i32_out_of_range(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) {
1013+
; CHECK-LABEL: uqshl_n_i32_out_of_range:
10261014
; CHECK: // %bb.0:
10271015
; CHECK-NEXT: mov z1.s, #32 // =0x20
10281016
; CHECK-NEXT: uqshl z0.s, p0/m, z0.s, z1.s
@@ -1033,8 +1021,8 @@ define <vscale x 4 x i32> @uqshl_n_i32_range(<vscale x 4 x i1> %pg, <vscale x 4
10331021
ret <vscale x 4 x i32> %out
10341022
}
10351023

1036-
define <vscale x 2 x i64> @uqshl_n_i64_range(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a) {
1037-
; CHECK-LABEL: uqshl_n_i64_range:
1024+
define <vscale x 2 x i64> @uqshl_n_i64_out_of_range(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a) {
1025+
; CHECK-LABEL: uqshl_n_i64_out_of_range:
10381026
; CHECK: // %bb.0:
10391027
; CHECK-NEXT: mov z1.d, #64 // =0x40
10401028
; CHECK-NEXT: uqshl z0.d, p0/m, z0.d, z1.d
@@ -1200,10 +1188,9 @@ define <vscale x 2 x i64> @urshl_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %
12001188
define <vscale x 16 x i8> @urshl_i8_swapped_operands(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
12011189
; CHECK-LABEL: urshl_i8_swapped_operands:
12021190
; CHECK: // %bb.0:
1203-
; CHECK-NEXT: ptrue p0.b
12041191
; CHECK-NEXT: urshlr z0.b, p0/m, z0.b, z1.b
12051192
; CHECK-NEXT: ret
1206-
%out = call <vscale x 16 x i8> @llvm.aarch64.sve.urshl.u.nxv16i8(<vscale x 16 x i1> splat(i1 true),
1193+
%out = call <vscale x 16 x i8> @llvm.aarch64.sve.urshl.u.nxv16i8(<vscale x 16 x i1> %pg,
12071194
<vscale x 16 x i8> %b,
12081195
<vscale x 16 x i8> %a)
12091196
ret <vscale x 16 x i8> %out
@@ -1212,10 +1199,9 @@ define <vscale x 16 x i8> @urshl_i8_swapped_operands(<vscale x 16 x i1> %pg, <vs
12121199
define <vscale x 8 x i16> @urshl_i16_swapped_operands(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
12131200
; CHECK-LABEL: urshl_i16_swapped_operands:
12141201
; CHECK: // %bb.0:
1215-
; CHECK-NEXT: ptrue p0.h
12161202
; CHECK-NEXT: urshlr z0.h, p0/m, z0.h, z1.h
12171203
; CHECK-NEXT: ret
1218-
%out = call <vscale x 8 x i16> @llvm.aarch64.sve.urshl.u.nxv8i16(<vscale x 8 x i1> splat(i1 true),
1204+
%out = call <vscale x 8 x i16> @llvm.aarch64.sve.urshl.u.nxv8i16(<vscale x 8 x i1> %pg,
12191205
<vscale x 8 x i16> %b,
12201206
<vscale x 8 x i16> %a)
12211207
ret <vscale x 8 x i16> %out
@@ -1224,10 +1210,9 @@ define <vscale x 8 x i16> @urshl_i16_swapped_operands(<vscale x 8 x i1> %pg, <vs
12241210
define <vscale x 4 x i32> @urshl_i32_swapped_operands(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
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; CHECK-LABEL: urshl_i32_swapped_operands:
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; CHECK: // %bb.0:
1227-
; CHECK-NEXT: ptrue p0.s
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; CHECK-NEXT: urshlr z0.s, p0/m, z0.s, z1.s
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; CHECK-NEXT: ret
1230-
%out = call <vscale x 4 x i32> @llvm.aarch64.sve.urshl.u.nxv4i32(<vscale x 4 x i1> splat(i1 true),
1215+
%out = call <vscale x 4 x i32> @llvm.aarch64.sve.urshl.u.nxv4i32(<vscale x 4 x i1> %pg,
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<vscale x 4 x i32> %b,
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<vscale x 4 x i32> %a)
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ret <vscale x 4 x i32> %out
@@ -1236,10 +1221,9 @@ define <vscale x 4 x i32> @urshl_i32_swapped_operands(<vscale x 4 x i1> %pg, <vs
12361221
define <vscale x 2 x i64> @urshl_i64_swapped_operands(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
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; CHECK-LABEL: urshl_i64_swapped_operands:
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; CHECK: // %bb.0:
1239-
; CHECK-NEXT: ptrue p0.d
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; CHECK-NEXT: urshlr z0.d, p0/m, z0.d, z1.d
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; CHECK-NEXT: ret
1242-
%out = call <vscale x 2 x i64> @llvm.aarch64.sve.urshl.u.nxv2i64(<vscale x 2 x i1> splat(i1 true),
1226+
%out = call <vscale x 2 x i64> @llvm.aarch64.sve.urshl.u.nxv2i64(<vscale x 2 x i1> %pg,
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<vscale x 2 x i64> %b,
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<vscale x 2 x i64> %a)
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ret <vscale x 2 x i64> %out

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