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[RISCV] Use ISD::XOR instead of RISCVISD::VMXOR_VL in lowerVectorMaskVecReduction of scalable ISD::VECREDUCE_AND (#121812)
This allows combining the XOR with earlier ISD::ANDs inserted by type legalization.
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2 files changed

+16
-25
lines changed

2 files changed

+16
-25
lines changed

‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp‎

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -10154,7 +10154,10 @@ SDValue RISCVTargetLowering::lowerVectorMaskVecReduction(SDValue Op,
1015410154
case ISD::VP_REDUCE_AND: {
1015510155
// vcpop ~x == 0
1015610156
SDValue TrueMask = DAG.getNode(RISCVISD::VMSET_VL, DL, ContainerVT, VL);
10157-
Vec = DAG.getNode(RISCVISD::VMXOR_VL, DL, ContainerVT, Vec, TrueMask, VL);
10157+
if (IsVP || VecVT.isFixedLengthVector())
10158+
Vec = DAG.getNode(RISCVISD::VMXOR_VL, DL, ContainerVT, Vec, TrueMask, VL);
10159+
else
10160+
Vec = DAG.getNode(ISD::XOR, DL, ContainerVT, Vec, TrueMask);
1015810161
Vec = DAG.getNode(RISCVISD::VCPOP_VL, DL, XLenVT, Vec, Mask, VL);
1015910162
CC = ISD::SETEQ;
1016010163
break;

‎llvm/test/CodeGen/RISCV/rvv/vreductions-mask.ll‎

Lines changed: 12 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -785,8 +785,7 @@ define zeroext i1 @vreduce_and_nxv128i1(<vscale x 128 x i1> %v) {
785785
; CHECK-LABEL: vreduce_and_nxv128i1:
786786
; CHECK: # %bb.0:
787787
; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma
788-
; CHECK-NEXT: vmand.mm v8, v0, v8
789-
; CHECK-NEXT: vmnot.m v8, v8
788+
; CHECK-NEXT: vmnand.mm v8, v0, v8
790789
; CHECK-NEXT: vcpop.m a0, v8
791790
; CHECK-NEXT: seqz a0, a0
792791
; CHECK-NEXT: ret
@@ -814,8 +813,7 @@ define zeroext i1 @vreduce_smax_nxv128i1(<vscale x 128 x i1> %v) {
814813
; CHECK-LABEL: vreduce_smax_nxv128i1:
815814
; CHECK: # %bb.0:
816815
; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma
817-
; CHECK-NEXT: vmand.mm v8, v0, v8
818-
; CHECK-NEXT: vmnot.m v8, v8
816+
; CHECK-NEXT: vmnand.mm v8, v0, v8
819817
; CHECK-NEXT: vcpop.m a0, v8
820818
; CHECK-NEXT: seqz a0, a0
821819
; CHECK-NEXT: ret
@@ -829,8 +827,7 @@ define zeroext i1 @vreduce_umin_nxv128i1(<vscale x 128 x i1> %v) {
829827
; CHECK-LABEL: vreduce_umin_nxv128i1:
830828
; CHECK: # %bb.0:
831829
; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma
832-
; CHECK-NEXT: vmand.mm v8, v0, v8
833-
; CHECK-NEXT: vmnot.m v8, v8
830+
; CHECK-NEXT: vmnand.mm v8, v0, v8
834831
; CHECK-NEXT: vcpop.m a0, v8
835832
; CHECK-NEXT: seqz a0, a0
836833
; CHECK-NEXT: ret
@@ -892,8 +889,7 @@ define zeroext i1 @vreduce_and_nxv256i1(<vscale x 256 x i1> %v) {
892889
; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma
893890
; CHECK-NEXT: vmand.mm v8, v8, v10
894891
; CHECK-NEXT: vmand.mm v9, v0, v9
895-
; CHECK-NEXT: vmand.mm v8, v9, v8
896-
; CHECK-NEXT: vmnot.m v8, v8
892+
; CHECK-NEXT: vmnand.mm v8, v9, v8
897893
; CHECK-NEXT: vcpop.m a0, v8
898894
; CHECK-NEXT: seqz a0, a0
899895
; CHECK-NEXT: ret
@@ -925,8 +921,7 @@ define zeroext i1 @vreduce_smax_nxv256i1(<vscale x 256 x i1> %v) {
925921
; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma
926922
; CHECK-NEXT: vmand.mm v8, v8, v10
927923
; CHECK-NEXT: vmand.mm v9, v0, v9
928-
; CHECK-NEXT: vmand.mm v8, v9, v8
929-
; CHECK-NEXT: vmnot.m v8, v8
924+
; CHECK-NEXT: vmnand.mm v8, v9, v8
930925
; CHECK-NEXT: vcpop.m a0, v8
931926
; CHECK-NEXT: seqz a0, a0
932927
; CHECK-NEXT: ret
@@ -942,8 +937,7 @@ define zeroext i1 @vreduce_umin_nxv256i1(<vscale x 256 x i1> %v) {
942937
; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma
943938
; CHECK-NEXT: vmand.mm v8, v8, v10
944939
; CHECK-NEXT: vmand.mm v9, v0, v9
945-
; CHECK-NEXT: vmand.mm v8, v9, v8
946-
; CHECK-NEXT: vmnot.m v8, v8
940+
; CHECK-NEXT: vmnand.mm v8, v9, v8
947941
; CHECK-NEXT: vcpop.m a0, v8
948942
; CHECK-NEXT: seqz a0, a0
949943
; CHECK-NEXT: ret
@@ -1019,8 +1013,7 @@ define zeroext i1 @vreduce_and_nxv512i1(<vscale x 512 x i1> %v) {
10191013
; CHECK-NEXT: vmand.mm v11, v0, v11
10201014
; CHECK-NEXT: vmand.mm v8, v8, v10
10211015
; CHECK-NEXT: vmand.mm v9, v11, v9
1022-
; CHECK-NEXT: vmand.mm v8, v9, v8
1023-
; CHECK-NEXT: vmnot.m v8, v8
1016+
; CHECK-NEXT: vmnand.mm v8, v9, v8
10241017
; CHECK-NEXT: vcpop.m a0, v8
10251018
; CHECK-NEXT: seqz a0, a0
10261019
; CHECK-NEXT: ret
@@ -1060,8 +1053,7 @@ define zeroext i1 @vreduce_smax_nxv512i1(<vscale x 512 x i1> %v) {
10601053
; CHECK-NEXT: vmand.mm v11, v0, v11
10611054
; CHECK-NEXT: vmand.mm v8, v8, v10
10621055
; CHECK-NEXT: vmand.mm v9, v11, v9
1063-
; CHECK-NEXT: vmand.mm v8, v9, v8
1064-
; CHECK-NEXT: vmnot.m v8, v8
1056+
; CHECK-NEXT: vmnand.mm v8, v9, v8
10651057
; CHECK-NEXT: vcpop.m a0, v8
10661058
; CHECK-NEXT: seqz a0, a0
10671059
; CHECK-NEXT: ret
@@ -1081,8 +1073,7 @@ define zeroext i1 @vreduce_umin_nxv512i1(<vscale x 512 x i1> %v) {
10811073
; CHECK-NEXT: vmand.mm v11, v0, v11
10821074
; CHECK-NEXT: vmand.mm v8, v8, v10
10831075
; CHECK-NEXT: vmand.mm v9, v11, v9
1084-
; CHECK-NEXT: vmand.mm v8, v9, v8
1085-
; CHECK-NEXT: vmnot.m v8, v8
1076+
; CHECK-NEXT: vmnand.mm v8, v9, v8
10861077
; CHECK-NEXT: vcpop.m a0, v8
10871078
; CHECK-NEXT: seqz a0, a0
10881079
; CHECK-NEXT: ret
@@ -1186,8 +1177,7 @@ define zeroext i1 @vreduce_and_nxv1024i1(<vscale x 1024 x i1> %v) {
11861177
; CHECK-NEXT: vmand.mm v11, v15, v11
11871178
; CHECK-NEXT: vmand.mm v8, v8, v10
11881179
; CHECK-NEXT: vmand.mm v9, v11, v9
1189-
; CHECK-NEXT: vmand.mm v8, v9, v8
1190-
; CHECK-NEXT: vmnot.m v8, v8
1180+
; CHECK-NEXT: vmnand.mm v8, v9, v8
11911181
; CHECK-NEXT: vcpop.m a0, v8
11921182
; CHECK-NEXT: seqz a0, a0
11931183
; CHECK-NEXT: ret
@@ -1243,8 +1233,7 @@ define zeroext i1 @vreduce_smax_nxv1024i1(<vscale x 1024 x i1> %v) {
12431233
; CHECK-NEXT: vmand.mm v11, v15, v11
12441234
; CHECK-NEXT: vmand.mm v8, v8, v10
12451235
; CHECK-NEXT: vmand.mm v9, v11, v9
1246-
; CHECK-NEXT: vmand.mm v8, v9, v8
1247-
; CHECK-NEXT: vmnot.m v8, v8
1236+
; CHECK-NEXT: vmnand.mm v8, v9, v8
12481237
; CHECK-NEXT: vcpop.m a0, v8
12491238
; CHECK-NEXT: seqz a0, a0
12501239
; CHECK-NEXT: ret
@@ -1272,8 +1261,7 @@ define zeroext i1 @vreduce_umin_nxv1024i1(<vscale x 1024 x i1> %v) {
12721261
; CHECK-NEXT: vmand.mm v11, v15, v11
12731262
; CHECK-NEXT: vmand.mm v8, v8, v10
12741263
; CHECK-NEXT: vmand.mm v9, v11, v9
1275-
; CHECK-NEXT: vmand.mm v8, v9, v8
1276-
; CHECK-NEXT: vmnot.m v8, v8
1264+
; CHECK-NEXT: vmnand.mm v8, v9, v8
12771265
; CHECK-NEXT: vcpop.m a0, v8
12781266
; CHECK-NEXT: seqz a0, a0
12791267
; CHECK-NEXT: ret

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