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[LoongArch][NFC] Add tests for combining and(add(not)) (#159055)
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‎llvm/test/CodeGen/LoongArch/lasx/and-not-combine.ll‎

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
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; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
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; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
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define void @and_not_combine_v32i8(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
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; CHECK-LABEL: and_not_combine_v32i8:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xvld $xr0, $a2, 0
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; CHECK-NEXT: xvld $xr1, $a3, 0
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; CHECK-NEXT: xvld $xr2, $a1, 0
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; CHECK-NEXT: xvxori.b $xr0, $xr0, 255
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; CHECK-NEXT: xvadd.b $xr0, $xr0, $xr1
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; CHECK-NEXT: xvand.v $xr0, $xr2, $xr0
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; CHECK-NEXT: xvst $xr0, $a0, 0
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; CHECK-NEXT: ret
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entry:
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%v0 = load <32 x i8>, ptr %a0
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%v1 = load <32 x i8>, ptr %a1
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%v2 = load <32 x i8>, ptr %a2
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%not = xor <32 x i8> %v1, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
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%add = add <32 x i8> %not, %v2
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%and = and <32 x i8> %v0, %add
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store <32 x i8> %and, ptr %res
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ret void
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}
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define void @and_not_combine_v16i16(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
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; CHECK-LABEL: and_not_combine_v16i16:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xvld $xr0, $a2, 0
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; CHECK-NEXT: xvld $xr1, $a3, 0
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; CHECK-NEXT: xvld $xr2, $a1, 0
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; CHECK-NEXT: xvrepli.b $xr3, -1
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; CHECK-NEXT: xvxor.v $xr0, $xr0, $xr3
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; CHECK-NEXT: xvadd.h $xr0, $xr0, $xr1
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; CHECK-NEXT: xvand.v $xr0, $xr2, $xr0
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; CHECK-NEXT: xvst $xr0, $a0, 0
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; CHECK-NEXT: ret
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entry:
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%v0 = load <16 x i16>, ptr %a0
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%v1 = load <16 x i16>, ptr %a1
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%v2 = load <16 x i16>, ptr %a2
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%not = xor <16 x i16> %v1, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
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%add = add <16 x i16> %not, %v2
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%and = and <16 x i16> %v0, %add
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store <16 x i16> %and, ptr %res
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ret void
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}
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define void @and_not_combine_v8i32(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
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; CHECK-LABEL: and_not_combine_v8i32:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xvld $xr0, $a2, 0
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; CHECK-NEXT: xvld $xr1, $a3, 0
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; CHECK-NEXT: xvld $xr2, $a1, 0
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; CHECK-NEXT: xvrepli.b $xr3, -1
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; CHECK-NEXT: xvxor.v $xr0, $xr0, $xr3
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; CHECK-NEXT: xvadd.w $xr0, $xr0, $xr1
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; CHECK-NEXT: xvand.v $xr0, $xr2, $xr0
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; CHECK-NEXT: xvst $xr0, $a0, 0
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; CHECK-NEXT: ret
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entry:
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%v0 = load <8 x i32>, ptr %a0
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%v1 = load <8 x i32>, ptr %a1
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%v2 = load <8 x i32>, ptr %a2
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%not = xor <8 x i32> %v1, <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>
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%add = add <8 x i32> %not, %v2
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%and = and <8 x i32> %v0, %add
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store <8 x i32> %and, ptr %res
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ret void
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}
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define void @and_not_combine_v4i64(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
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; CHECK-LABEL: and_not_combine_v4i64:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xvld $xr0, $a2, 0
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; CHECK-NEXT: xvld $xr1, $a3, 0
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; CHECK-NEXT: xvld $xr2, $a1, 0
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; CHECK-NEXT: xvrepli.b $xr3, -1
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; CHECK-NEXT: xvxor.v $xr0, $xr0, $xr3
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; CHECK-NEXT: xvadd.d $xr0, $xr0, $xr1
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; CHECK-NEXT: xvand.v $xr0, $xr2, $xr0
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; CHECK-NEXT: xvst $xr0, $a0, 0
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; CHECK-NEXT: ret
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entry:
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%v0 = load <4 x i64>, ptr %a0
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%v1 = load <4 x i64>, ptr %a1
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%v2 = load <4 x i64>, ptr %a2
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%not = xor <4 x i64> %v1, <i64 -1, i64 -1, i64 -1, i64 -1>
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%add = add <4 x i64> %not, %v2
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%and = and <4 x i64> %v0, %add
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store <4 x i64> %and, ptr %res
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ret void
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}

‎llvm/test/CodeGen/LoongArch/lsx/and-not-combine.ll‎

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
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; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
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; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
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define void @and_not_combine_v16i8(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
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; CHECK-LABEL: and_not_combine_v16i8:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vld $vr0, $a2, 0
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; CHECK-NEXT: vld $vr1, $a3, 0
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; CHECK-NEXT: vld $vr2, $a1, 0
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; CHECK-NEXT: vxori.b $vr0, $vr0, 255
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; CHECK-NEXT: vadd.b $vr0, $vr0, $vr1
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; CHECK-NEXT: vand.v $vr0, $vr2, $vr0
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; CHECK-NEXT: vst $vr0, $a0, 0
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; CHECK-NEXT: ret
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entry:
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%v0 = load <16 x i8>, ptr %a0
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%v1 = load <16 x i8>, ptr %a1
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%v2 = load <16 x i8>, ptr %a2
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%not = xor <16 x i8> %v1, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
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%add = add <16 x i8> %not, %v2
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%and = and <16 x i8> %v0, %add
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store <16 x i8> %and, ptr %res
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ret void
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}
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define void @and_not_combine_v8i16(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
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; CHECK-LABEL: and_not_combine_v8i16:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vld $vr0, $a2, 0
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; CHECK-NEXT: vld $vr1, $a3, 0
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; CHECK-NEXT: vld $vr2, $a1, 0
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; CHECK-NEXT: vrepli.b $vr3, -1
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; CHECK-NEXT: vxor.v $vr0, $vr0, $vr3
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; CHECK-NEXT: vadd.h $vr0, $vr0, $vr1
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; CHECK-NEXT: vand.v $vr0, $vr2, $vr0
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; CHECK-NEXT: vst $vr0, $a0, 0
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; CHECK-NEXT: ret
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entry:
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%v0 = load <8 x i16>, ptr %a0
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%v1 = load <8 x i16>, ptr %a1
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%v2 = load <8 x i16>, ptr %a2
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%not = xor <8 x i16> %v1, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
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%add = add <8 x i16> %not, %v2
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%and = and <8 x i16> %v0, %add
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store <8 x i16> %and, ptr %res
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ret void
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}
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define void @and_not_combine_v4i32(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
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; CHECK-LABEL: and_not_combine_v4i32:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vld $vr0, $a2, 0
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; CHECK-NEXT: vld $vr1, $a3, 0
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; CHECK-NEXT: vld $vr2, $a1, 0
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; CHECK-NEXT: vrepli.b $vr3, -1
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; CHECK-NEXT: vxor.v $vr0, $vr0, $vr3
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; CHECK-NEXT: vadd.w $vr0, $vr0, $vr1
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; CHECK-NEXT: vand.v $vr0, $vr2, $vr0
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; CHECK-NEXT: vst $vr0, $a0, 0
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; CHECK-NEXT: ret
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entry:
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%v0 = load <4 x i32>, ptr %a0
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%v1 = load <4 x i32>, ptr %a1
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%v2 = load <4 x i32>, ptr %a2
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%not = xor <4 x i32> %v1, <i32 -1, i32 -1, i32 -1, i32 -1>
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%add = add <4 x i32> %not, %v2
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%and = and <4 x i32> %v0, %add
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store <4 x i32> %and, ptr %res
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ret void
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}
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define void @and_not_combine_v2i64(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
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; CHECK-LABEL: and_not_combine_v2i64:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vld $vr0, $a2, 0
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; CHECK-NEXT: vld $vr1, $a3, 0
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; CHECK-NEXT: vld $vr2, $a1, 0
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; CHECK-NEXT: vrepli.b $vr3, -1
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; CHECK-NEXT: vxor.v $vr0, $vr0, $vr3
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; CHECK-NEXT: vadd.d $vr0, $vr0, $vr1
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; CHECK-NEXT: vand.v $vr0, $vr2, $vr0
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; CHECK-NEXT: vst $vr0, $a0, 0
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; CHECK-NEXT: ret
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entry:
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%v0 = load <2 x i64>, ptr %a0
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%v1 = load <2 x i64>, ptr %a1
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%v2 = load <2 x i64>, ptr %a2
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%not = xor <2 x i64> %v1, <i64 -1, i64 -1>
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%add = add <2 x i64> %not, %v2
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%and = and <2 x i64> %v0, %add
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store <2 x i64> %and, ptr %res
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ret void
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}

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