@@ -1521,13 +1521,13 @@ class VPseudoTiedBinaryMaskRoundingMode<VReg RetClass,
15211521 let UsesVXRM = 0;
15221522}
15231523
1524- class VPseudoBinaryCarryIn <VReg RetClass,
1525- VReg Op1Class,
1526- DAGOperand Op2Class,
1527- LMULInfo MInfo,
1528- bit CarryIn,
1529- string Constraint,
1530- int TargetConstraintType = 1> :
1524+ class VPseudoBinaryCarry <VReg RetClass,
1525+ VReg Op1Class,
1526+ DAGOperand Op2Class,
1527+ LMULInfo MInfo,
1528+ bit CarryIn,
1529+ string Constraint,
1530+ int TargetConstraintType = 1> :
15311531 Pseudo<(outs RetClass:$rd),
15321532 !if(CarryIn,
15331533 (ins Op1Class:$rs2, Op2Class:$rs1,
@@ -2454,10 +2454,10 @@ multiclass VPseudoBinaryV_VM<LMULInfo m, bit CarryOut = 0, bit CarryIn = 1,
24542454 int TargetConstraintType = 1> {
24552455 let isCommutable = Commutable in
24562456 def "_VV" # !if(CarryIn, "M", "") # "_" # m.MX :
2457- VPseudoBinaryCarryIn <!if(CarryOut, VR,
2458- !if(!and(CarryIn, !not(CarryOut)),
2459- GetVRegNoV0<m.vrclass>.R, m.vrclass)),
2460- m.vrclass, m.vrclass, m, CarryIn, Constraint, TargetConstraintType>;
2457+ VPseudoBinaryCarry <!if(CarryOut, VR,
2458+ !if(!and(CarryIn, !not(CarryOut)),
2459+ GetVRegNoV0<m.vrclass>.R, m.vrclass)),
2460+ m.vrclass, m.vrclass, m, CarryIn, Constraint, TargetConstraintType>;
24612461}
24622462
24632463multiclass VPseudoTiedBinaryV_VM<LMULInfo m, bit Commutable = 0> {
@@ -2470,10 +2470,10 @@ multiclass VPseudoTiedBinaryV_VM<LMULInfo m, bit Commutable = 0> {
24702470multiclass VPseudoBinaryV_XM<LMULInfo m, bit CarryOut = 0, bit CarryIn = 1,
24712471 string Constraint = "", int TargetConstraintType = 1> {
24722472 def "_VX" # !if(CarryIn, "M", "") # "_" # m.MX :
2473- VPseudoBinaryCarryIn <!if(CarryOut, VR,
2474- !if(!and(CarryIn, !not(CarryOut)),
2475- GetVRegNoV0<m.vrclass>.R, m.vrclass)),
2476- m.vrclass, GPR, m, CarryIn, Constraint, TargetConstraintType>;
2473+ VPseudoBinaryCarry <!if(CarryOut, VR,
2474+ !if(!and(CarryIn, !not(CarryOut)),
2475+ GetVRegNoV0<m.vrclass>.R, m.vrclass)),
2476+ m.vrclass, GPR, m, CarryIn, Constraint, TargetConstraintType>;
24772477}
24782478
24792479multiclass VPseudoTiedBinaryV_XM<LMULInfo m> {
@@ -2498,10 +2498,10 @@ multiclass VPseudoVMRG_FM {
24982498multiclass VPseudoBinaryV_IM<LMULInfo m, bit CarryOut = 0, bit CarryIn = 1,
24992499 string Constraint = "", int TargetConstraintType = 1> {
25002500 def "_VI" # !if(CarryIn, "M", "") # "_" # m.MX :
2501- VPseudoBinaryCarryIn <!if(CarryOut, VR,
2502- !if(!and(CarryIn, !not(CarryOut)),
2503- GetVRegNoV0<m.vrclass>.R, m.vrclass)),
2504- m.vrclass, simm5, m, CarryIn, Constraint, TargetConstraintType>;
2501+ VPseudoBinaryCarry <!if(CarryOut, VR,
2502+ !if(!and(CarryIn, !not(CarryOut)),
2503+ GetVRegNoV0<m.vrclass>.R, m.vrclass)),
2504+ m.vrclass, simm5, m, CarryIn, Constraint, TargetConstraintType>;
25052505}
25062506
25072507multiclass VPseudoTiedBinaryV_IM<LMULInfo m> {
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