Add brackets to nested ternary expression

hazzlim · hazzlim · commit c917f7739f44 · 2024-12-13T11:44:18.000Z
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -18608,9 +18608,9 @@ static SDValue performBuildShuffleExtendCombine(SDValue BV, SelectionDAG &DAG) {
                                    : BV.getOperand(1).getOperand(0),
                                cast<ShuffleVectorSDNode>(BV)->getMask());
   }
-  unsigned ExtOpc = !SeenZExtOrSExt ? ISD::ANY_EXTEND
-                    : IsSExt        ? ISD::SIGN_EXTEND
-                                    : ISD::ZERO_EXTEND;
+  unsigned ExtOpc = !SeenZExtOrSExt
+                        ? ISD::ANY_EXTEND
+                        : (IsSExt ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND);
   return DAG.getNode(ExtOpc, DL, VT, NBV);
 }
 

Original file line number	Diff line number	Diff line change
`@@ -18608,9 +18608,9 @@ static SDValue performBuildShuffleExtendCombine(SDValue BV, SelectionDAG &DAG) {`
`18608`	`18608`	`: BV.getOperand(1).getOperand(0),`
`18609`	`18609`	`cast<ShuffleVectorSDNode>(BV)->getMask());`
`18610`	`18610`	`}`
`18611`		`- unsigned ExtOpc = !SeenZExtOrSExt ? ISD::ANY_EXTEND`
`18612`		`- : IsSExt ? ISD::SIGN_EXTEND`
`18613`		`- : ISD::ZERO_EXTEND;`
	`18611`	`+ unsigned ExtOpc = !SeenZExtOrSExt`
	`18612`	`+ ? ISD::ANY_EXTEND`
	`18613`	`+ : (IsSExt ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND);`
`18614`	`18614`	`return DAG.getNode(ExtOpc, DL, VT, NBV);`
`18615`	`18615`	`}`
`18616`	`18616`