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[X86] Consistently use 'k' for predicate mask registers in instruction names (#108780)
We use 'k' for move instructions and to indicate masked variants of evex instructions, but otherwise we're very inconsistent when we use 'k' vs 'r'.
1 parent c970e96 commit c91f2a2

13 files changed

+277
-277
lines changed

‎llvm/lib/Target/X86/X86DomainReassignment.cpp

Lines changed: 62 additions & 62 deletions
Original file line numberDiff line numberDiff line change
@@ -636,21 +636,21 @@ void X86DomainReassignment::initConverters() {
636636
createReplacer(X86::MOV16rm, GET_EGPR_IF_ENABLED(X86::KMOVWkm));
637637
createReplacer(X86::MOV16mr, GET_EGPR_IF_ENABLED(X86::KMOVWmk));
638638
createReplacer(X86::MOV16rr, GET_EGPR_IF_ENABLED(X86::KMOVWkk));
639-
createReplacer(X86::SHR16ri, X86::KSHIFTRWri);
640-
createReplacer(X86::SHL16ri, X86::KSHIFTLWri);
641-
createReplacer(X86::NOT16r, X86::KNOTWrr);
642-
createReplacer(X86::OR16rr, X86::KORWrr);
643-
createReplacer(X86::AND16rr, X86::KANDWrr);
644-
createReplacer(X86::XOR16rr, X86::KXORWrr);
639+
createReplacer(X86::SHR16ri, X86::KSHIFTRWki);
640+
createReplacer(X86::SHL16ri, X86::KSHIFTLWki);
641+
createReplacer(X86::NOT16r, X86::KNOTWkk);
642+
createReplacer(X86::OR16rr, X86::KORWkk);
643+
createReplacer(X86::AND16rr, X86::KANDWkk);
644+
createReplacer(X86::XOR16rr, X86::KXORWkk);
645645

646646
bool HasNDD = STI->hasNDD();
647647
if (HasNDD) {
648-
createReplacer(X86::SHR16ri_ND, X86::KSHIFTRWri);
649-
createReplacer(X86::SHL16ri_ND, X86::KSHIFTLWri);
650-
createReplacer(X86::NOT16r_ND, X86::KNOTWrr);
651-
createReplacer(X86::OR16rr_ND, X86::KORWrr);
652-
createReplacer(X86::AND16rr_ND, X86::KANDWrr);
653-
createReplacer(X86::XOR16rr_ND, X86::KXORWrr);
648+
createReplacer(X86::SHR16ri_ND, X86::KSHIFTRWki);
649+
createReplacer(X86::SHL16ri_ND, X86::KSHIFTLWki);
650+
createReplacer(X86::NOT16r_ND, X86::KNOTWkk);
651+
createReplacer(X86::OR16rr_ND, X86::KORWkk);
652+
createReplacer(X86::AND16rr_ND, X86::KANDWkk);
653+
createReplacer(X86::XOR16rr_ND, X86::KXORWkk);
654654
}
655655

656656
if (STI->hasBWI()) {
@@ -663,86 +663,86 @@ void X86DomainReassignment::initConverters() {
663663
createReplacer(X86::MOV32rr, GET_EGPR_IF_ENABLED(X86::KMOVDkk));
664664
createReplacer(X86::MOV64rr, GET_EGPR_IF_ENABLED(X86::KMOVQkk));
665665

666-
createReplacer(X86::SHR32ri, X86::KSHIFTRDri);
667-
createReplacer(X86::SHR64ri, X86::KSHIFTRQri);
666+
createReplacer(X86::SHR32ri, X86::KSHIFTRDki);
667+
createReplacer(X86::SHR64ri, X86::KSHIFTRQki);
668668

669-
createReplacer(X86::SHL32ri, X86::KSHIFTLDri);
670-
createReplacer(X86::SHL64ri, X86::KSHIFTLQri);
669+
createReplacer(X86::SHL32ri, X86::KSHIFTLDki);
670+
createReplacer(X86::SHL64ri, X86::KSHIFTLQki);
671671

672-
createReplacer(X86::ADD32rr, X86::KADDDrr);
673-
createReplacer(X86::ADD64rr, X86::KADDQrr);
672+
createReplacer(X86::ADD32rr, X86::KADDDkk);
673+
createReplacer(X86::ADD64rr, X86::KADDQkk);
674674

675-
createReplacer(X86::NOT32r, X86::KNOTDrr);
676-
createReplacer(X86::NOT64r, X86::KNOTQrr);
675+
createReplacer(X86::NOT32r, X86::KNOTDkk);
676+
createReplacer(X86::NOT64r, X86::KNOTQkk);
677677

678-
createReplacer(X86::OR32rr, X86::KORDrr);
679-
createReplacer(X86::OR64rr, X86::KORQrr);
678+
createReplacer(X86::OR32rr, X86::KORDkk);
679+
createReplacer(X86::OR64rr, X86::KORQkk);
680680

681-
createReplacer(X86::AND32rr, X86::KANDDrr);
682-
createReplacer(X86::AND64rr, X86::KANDQrr);
681+
createReplacer(X86::AND32rr, X86::KANDDkk);
682+
createReplacer(X86::AND64rr, X86::KANDQkk);
683683

684-
createReplacer(X86::ANDN32rr, X86::KANDNDrr);
685-
createReplacer(X86::ANDN64rr, X86::KANDNQrr);
684+
createReplacer(X86::ANDN32rr, X86::KANDNDkk);
685+
createReplacer(X86::ANDN64rr, X86::KANDNQkk);
686686

687-
createReplacer(X86::XOR32rr, X86::KXORDrr);
688-
createReplacer(X86::XOR64rr, X86::KXORQrr);
687+
createReplacer(X86::XOR32rr, X86::KXORDkk);
688+
createReplacer(X86::XOR64rr, X86::KXORQkk);
689689

690690
if (HasNDD) {
691-
createReplacer(X86::SHR32ri_ND, X86::KSHIFTRDri);
692-
createReplacer(X86::SHL32ri_ND, X86::KSHIFTLDri);
693-
createReplacer(X86::ADD32rr_ND, X86::KADDDrr);
694-
createReplacer(X86::NOT32r_ND, X86::KNOTDrr);
695-
createReplacer(X86::OR32rr_ND, X86::KORDrr);
696-
createReplacer(X86::AND32rr_ND, X86::KANDDrr);
697-
createReplacer(X86::XOR32rr_ND, X86::KXORDrr);
698-
createReplacer(X86::SHR64ri_ND, X86::KSHIFTRQri);
699-
createReplacer(X86::SHL64ri_ND, X86::KSHIFTLQri);
700-
createReplacer(X86::ADD64rr_ND, X86::KADDQrr);
701-
createReplacer(X86::NOT64r_ND, X86::KNOTQrr);
702-
createReplacer(X86::OR64rr_ND, X86::KORQrr);
703-
createReplacer(X86::AND64rr_ND, X86::KANDQrr);
704-
createReplacer(X86::XOR64rr_ND, X86::KXORQrr);
691+
createReplacer(X86::SHR32ri_ND, X86::KSHIFTRDki);
692+
createReplacer(X86::SHL32ri_ND, X86::KSHIFTLDki);
693+
createReplacer(X86::ADD32rr_ND, X86::KADDDkk);
694+
createReplacer(X86::NOT32r_ND, X86::KNOTDkk);
695+
createReplacer(X86::OR32rr_ND, X86::KORDkk);
696+
createReplacer(X86::AND32rr_ND, X86::KANDDkk);
697+
createReplacer(X86::XOR32rr_ND, X86::KXORDkk);
698+
createReplacer(X86::SHR64ri_ND, X86::KSHIFTRQki);
699+
createReplacer(X86::SHL64ri_ND, X86::KSHIFTLQki);
700+
createReplacer(X86::ADD64rr_ND, X86::KADDQkk);
701+
createReplacer(X86::NOT64r_ND, X86::KNOTQkk);
702+
createReplacer(X86::OR64rr_ND, X86::KORQkk);
703+
createReplacer(X86::AND64rr_ND, X86::KANDQkk);
704+
createReplacer(X86::XOR64rr_ND, X86::KXORQkk);
705705
}
706706

707707
// TODO: KTEST is not a replacement for TEST due to flag differences. Need
708708
// to prove only Z flag is used.
709-
// createReplacer(X86::TEST32rr, X86::KTESTDrr);
710-
// createReplacer(X86::TEST64rr, X86::KTESTQrr);
709+
// createReplacer(X86::TEST32rr, X86::KTESTDkk);
710+
// createReplacer(X86::TEST64rr, X86::KTESTQkk);
711711
}
712712

713713
if (STI->hasDQI()) {
714-
createReplacer(X86::ADD8rr, X86::KADDBrr);
715-
createReplacer(X86::ADD16rr, X86::KADDWrr);
714+
createReplacer(X86::ADD8rr, X86::KADDBkk);
715+
createReplacer(X86::ADD16rr, X86::KADDWkk);
716716

717-
createReplacer(X86::AND8rr, X86::KANDBrr);
717+
createReplacer(X86::AND8rr, X86::KANDBkk);
718718

719719
createReplacer(X86::MOV8rm, GET_EGPR_IF_ENABLED(X86::KMOVBkm));
720720
createReplacer(X86::MOV8mr, GET_EGPR_IF_ENABLED(X86::KMOVBmk));
721721
createReplacer(X86::MOV8rr, GET_EGPR_IF_ENABLED(X86::KMOVBkk));
722722

723-
createReplacer(X86::NOT8r, X86::KNOTBrr);
723+
createReplacer(X86::NOT8r, X86::KNOTBkk);
724724

725-
createReplacer(X86::OR8rr, X86::KORBrr);
725+
createReplacer(X86::OR8rr, X86::KORBkk);
726726

727-
createReplacer(X86::SHR8ri, X86::KSHIFTRBri);
728-
createReplacer(X86::SHL8ri, X86::KSHIFTLBri);
727+
createReplacer(X86::SHR8ri, X86::KSHIFTRBki);
728+
createReplacer(X86::SHL8ri, X86::KSHIFTLBki);
729729

730730
// TODO: KTEST is not a replacement for TEST due to flag differences. Need
731731
// to prove only Z flag is used.
732-
// createReplacer(X86::TEST8rr, X86::KTESTBrr);
733-
// createReplacer(X86::TEST16rr, X86::KTESTWrr);
732+
// createReplacer(X86::TEST8rr, X86::KTESTBkk);
733+
// createReplacer(X86::TEST16rr, X86::KTESTWkk);
734734

735-
createReplacer(X86::XOR8rr, X86::KXORBrr);
735+
createReplacer(X86::XOR8rr, X86::KXORBkk);
736736

737737
if (HasNDD) {
738-
createReplacer(X86::ADD8rr_ND, X86::KADDBrr);
739-
createReplacer(X86::ADD16rr_ND, X86::KADDWrr);
740-
createReplacer(X86::AND8rr_ND, X86::KANDBrr);
741-
createReplacer(X86::NOT8r_ND, X86::KNOTBrr);
742-
createReplacer(X86::OR8rr_ND, X86::KORBrr);
743-
createReplacer(X86::SHR8ri_ND, X86::KSHIFTRBri);
744-
createReplacer(X86::SHL8ri_ND, X86::KSHIFTLBri);
745-
createReplacer(X86::XOR8rr_ND, X86::KXORBrr);
738+
createReplacer(X86::ADD8rr_ND, X86::KADDBkk);
739+
createReplacer(X86::ADD16rr_ND, X86::KADDWkk);
740+
createReplacer(X86::AND8rr_ND, X86::KANDBkk);
741+
createReplacer(X86::NOT8r_ND, X86::KNOTBkk);
742+
createReplacer(X86::OR8rr_ND, X86::KORBkk);
743+
createReplacer(X86::SHR8ri_ND, X86::KSHIFTRBki);
744+
createReplacer(X86::SHL8ri_ND, X86::KSHIFTLBki);
745+
createReplacer(X86::XOR8rr_ND, X86::KXORBkk);
746746
}
747747
}
748748
#undef GET_EGPR_IF_ENABLED

‎llvm/lib/Target/X86/X86ISelDAGToDAG.cpp

Lines changed: 13 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -1647,10 +1647,10 @@ void X86DAGToDAGISel::PostprocessISelDAG() {
16471647
// used. We're doing this late so we can prefer to fold the AND into masked
16481648
// comparisons. Doing that can be better for the live range of the mask
16491649
// register.
1650-
case X86::KORTESTBrr:
1651-
case X86::KORTESTWrr:
1652-
case X86::KORTESTDrr:
1653-
case X86::KORTESTQrr: {
1650+
case X86::KORTESTBkk:
1651+
case X86::KORTESTWkk:
1652+
case X86::KORTESTDkk:
1653+
case X86::KORTESTQkk: {
16541654
SDValue Op0 = N->getOperand(0);
16551655
if (Op0 != N->getOperand(1) || !N->isOnlyUserOf(Op0.getNode()) ||
16561656
!Op0.isMachineOpcode() || !onlyUsesZeroFlag(SDValue(N, 0)))
@@ -1661,25 +1661,25 @@ void X86DAGToDAGISel::PostprocessISelDAG() {
16611661
switch (Op0.getMachineOpcode()) {
16621662
default:
16631663
continue;
1664-
CASE(KANDBrr)
1665-
CASE(KANDWrr)
1666-
CASE(KANDDrr)
1667-
CASE(KANDQrr)
1664+
CASE(KANDBkk)
1665+
CASE(KANDWkk)
1666+
CASE(KANDDkk)
1667+
CASE(KANDQkk)
16681668
}
16691669
unsigned NewOpc;
16701670
#define FROM_TO(A, B) \
16711671
case X86::A: \
16721672
NewOpc = X86::B; \
16731673
break;
16741674
switch (Opc) {
1675-
FROM_TO(KORTESTBrr, KTESTBrr)
1676-
FROM_TO(KORTESTWrr, KTESTWrr)
1677-
FROM_TO(KORTESTDrr, KTESTDrr)
1678-
FROM_TO(KORTESTQrr, KTESTQrr)
1675+
FROM_TO(KORTESTBkk, KTESTBkk)
1676+
FROM_TO(KORTESTWkk, KTESTWkk)
1677+
FROM_TO(KORTESTDkk, KTESTDkk)
1678+
FROM_TO(KORTESTQkk, KTESTQkk)
16791679
}
16801680
// KANDW is legal with AVX512F, but KTESTW requires AVX512DQ. The other
16811681
// KAND instructions and KTEST use the same ISA feature.
1682-
if (NewOpc == X86::KTESTWrr && !Subtarget->hasDQI())
1682+
if (NewOpc == X86::KTESTWkk && !Subtarget->hasDQI())
16831683
continue;
16841684
#undef FROM_TO
16851685
MachineSDNode *KTest = CurDAG->getMachineNode(

‎llvm/lib/Target/X86/X86InstrAVX512.td

Lines changed: 23 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -2782,7 +2782,7 @@ multiclass avx512_mask_unop<bits<8> opc, string OpcodeStr,
27822782
RegisterClass KRC, SDPatternOperator OpNode,
27832783
X86FoldableSchedWrite sched, Predicate prd> {
27842784
let Predicates = [prd] in
2785-
def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
2785+
def kk : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
27862786
!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
27872787
[(set KRC:$dst, (OpNode KRC:$src))]>,
27882788
Sched<[sched]>;
@@ -2807,14 +2807,14 @@ defm KNOT : avx512_mask_unop_all<0x44, "knot", vnot, SchedWriteVecLogic.XMM>;
28072807
// KNL does not support KMOVB, 8-bit mask is promoted to 16-bit
28082808
let Predicates = [HasAVX512, NoDQI] in
28092809
def : Pat<(vnot VK8:$src),
2810-
(COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$src, VK16)), VK8)>;
2810+
(COPY_TO_REGCLASS (KNOTWkk (COPY_TO_REGCLASS VK8:$src, VK16)), VK8)>;
28112811

28122812
def : Pat<(vnot VK4:$src),
2813-
(COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK4:$src, VK16)), VK4)>;
2813+
(COPY_TO_REGCLASS (KNOTWkk (COPY_TO_REGCLASS VK4:$src, VK16)), VK4)>;
28142814
def : Pat<(vnot VK2:$src),
2815-
(COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK2:$src, VK16)), VK2)>;
2815+
(COPY_TO_REGCLASS (KNOTWkk (COPY_TO_REGCLASS VK2:$src, VK16)), VK2)>;
28162816
def : Pat<(vnot VK1:$src),
2817-
(COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK1:$src, VK16)), VK2)>;
2817+
(COPY_TO_REGCLASS (KNOTWkk (COPY_TO_REGCLASS VK1:$src, VK16)), VK2)>;
28182818

28192819
// Mask binary operation
28202820
// - KAND, KANDN, KOR, KXNOR, KXOR
@@ -2823,7 +2823,7 @@ multiclass avx512_mask_binop<bits<8> opc, string OpcodeStr,
28232823
X86FoldableSchedWrite sched, Predicate prd,
28242824
bit IsCommutable> {
28252825
let Predicates = [prd], isCommutable = IsCommutable in
2826-
def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
2826+
def kk : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
28272827
!strconcat(OpcodeStr,
28282828
"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
28292829
[(set KRC:$dst, (OpNode KRC:$src1, KRC:$src2))]>,
@@ -2877,25 +2877,25 @@ multiclass avx512_binop_pat<SDPatternOperator VOpNode,
28772877
(COPY_TO_REGCLASS VK4:$src2, VK16)), VK4)>;
28782878
}
28792879

2880-
defm : avx512_binop_pat<and, KANDWrr>;
2881-
defm : avx512_binop_pat<vandn, KANDNWrr>;
2882-
defm : avx512_binop_pat<or, KORWrr>;
2883-
defm : avx512_binop_pat<vxnor, KXNORWrr>;
2884-
defm : avx512_binop_pat<xor, KXORWrr>;
2880+
defm : avx512_binop_pat<and, KANDWkk>;
2881+
defm : avx512_binop_pat<vandn, KANDNWkk>;
2882+
defm : avx512_binop_pat<or, KORWkk>;
2883+
defm : avx512_binop_pat<vxnor, KXNORWkk>;
2884+
defm : avx512_binop_pat<xor, KXORWkk>;
28852885

28862886
// Mask unpacking
28872887
multiclass avx512_mask_unpck<string Suffix, X86KVectorVTInfo Dst,
28882888
X86KVectorVTInfo Src, X86FoldableSchedWrite sched,
28892889
Predicate prd> {
28902890
let Predicates = [prd] in {
28912891
let hasSideEffects = 0 in
2892-
def rr : I<0x4b, MRMSrcReg, (outs Dst.KRC:$dst),
2892+
def kk : I<0x4b, MRMSrcReg, (outs Dst.KRC:$dst),
28932893
(ins Src.KRC:$src1, Src.KRC:$src2),
28942894
"kunpck"#Suffix#"\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
28952895
VEX, VVVV, VEX_L, Sched<[sched]>;
28962896

28972897
def : Pat<(Dst.KVT (concat_vectors Src.KRC:$src1, Src.KRC:$src2)),
2898-
(!cast<Instruction>(NAME#rr) Src.KRC:$src2, Src.KRC:$src1)>;
2898+
(!cast<Instruction>(NAME#kk) Src.KRC:$src2, Src.KRC:$src1)>;
28992899
}
29002900
}
29012901

@@ -2908,7 +2908,7 @@ multiclass avx512_mask_testop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
29082908
SDNode OpNode, X86FoldableSchedWrite sched,
29092909
Predicate prd> {
29102910
let Predicates = [prd], Defs = [EFLAGS] in
2911-
def rr : I<opc, MRMSrcReg, (outs), (ins KRC:$src1, KRC:$src2),
2911+
def kk : I<opc, MRMSrcReg, (outs), (ins KRC:$src1, KRC:$src2),
29122912
!strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
29132913
[(set EFLAGS, (OpNode KRC:$src1, KRC:$src2))]>,
29142914
Sched<[sched]>;
@@ -2935,7 +2935,7 @@ defm KTEST : avx512_mask_testop_w<0x99, "ktest", X86ktest, SchedWriteVecLogic.
29352935
multiclass avx512_mask_shiftop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
29362936
SDNode OpNode, X86FoldableSchedWrite sched> {
29372937
let Predicates = [HasAVX512] in
2938-
def ri : Ii8<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src, u8imm:$imm),
2938+
def ki : Ii8<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src, u8imm:$imm),
29392939
!strconcat(OpcodeStr,
29402940
"\t{$imm, $src, $dst|$dst, $src, $imm}"),
29412941
[(set KRC:$dst, (OpNode KRC:$src, (i8 timm:$imm)))]>,
@@ -3463,12 +3463,12 @@ def VMOVUPSZ256mr_NOVLX : I<0, Pseudo, (outs), (ins f256mem:$dst, VR256X:$src),
34633463

34643464
def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 immAllZerosV),
34653465
(v8i64 VR512:$src))),
3466-
(VMOVDQA64Zrrkz (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$mask, VK16)),
3466+
(VMOVDQA64Zrrkz (COPY_TO_REGCLASS (KNOTWkk (COPY_TO_REGCLASS VK8:$mask, VK16)),
34673467
VK8), VR512:$src)>;
34683468

34693469
def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 immAllZerosV),
34703470
(v16i32 VR512:$src))),
3471-
(VMOVDQA32Zrrkz (KNOTWrr VK16WM:$mask), VR512:$src)>;
3471+
(VMOVDQA32Zrrkz (KNOTWkk VK16WM:$mask), VR512:$src)>;
34723472

34733473
// These patterns exist to prevent the above patterns from introducing a second
34743474
// mask inversion when one already exists.
@@ -10425,7 +10425,7 @@ defm VSCATTERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qpd
1042510425
VK8WM, vz512mem>, EVEX_V512, REX_W, EVEX_CD8<64, CD8VT1>;
1042610426

1042710427
multiclass cvt_by_vec_width<bits<8> opc, X86VectorVTInfo Vec, string OpcodeStr, SchedWrite Sched> {
10428-
def rr : AVX512XS8I<opc, MRMSrcReg, (outs Vec.RC:$dst), (ins Vec.KRC:$src),
10428+
def rk : AVX512XS8I<opc, MRMSrcReg, (outs Vec.RC:$dst), (ins Vec.KRC:$src),
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!strconcat(OpcodeStr#Vec.Suffix, "\t{$src, $dst|$dst, $src}"),
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[(set Vec.RC:$dst, (Vec.VT (sext Vec.KRC:$src)))]>,
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EVEX, Sched<[Sched]>;
@@ -10448,7 +10448,7 @@ defm VPMOVM2D : cvt_mask_by_elt_width<0x38, avx512vl_i32_info, "vpmovm2", HasDQI
1044810448
defm VPMOVM2Q : cvt_mask_by_elt_width<0x38, avx512vl_i64_info, "vpmovm2", HasDQI> , REX_W;
1044910449

1045010450
multiclass convert_vector_to_mask_common<bits<8> opc, X86VectorVTInfo _, string OpcodeStr > {
10451-
def rr : AVX512XS8I<opc, MRMSrcReg, (outs _.KRC:$dst), (ins _.RC:$src),
10451+
def kr : AVX512XS8I<opc, MRMSrcReg, (outs _.KRC:$dst), (ins _.RC:$src),
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!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
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[(set _.KRC:$dst, (X86pcmpgtm _.ImmAllZerosV, (_.VT _.RC:$src)))]>,
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EVEX, Sched<[WriteMove]>;
@@ -10461,7 +10461,7 @@ multiclass convert_vector_to_mask_lowering<X86VectorVTInfo ExtendInfo,
1046110461

1046210462
def : Pat<(_.KVT (X86pcmpgtm _.ImmAllZerosV, (_.VT _.RC:$src))),
1046310463
(_.KVT (COPY_TO_REGCLASS
10464-
(!cast<Instruction>(Name#"Zrr")
10464+
(!cast<Instruction>(Name#"Zkr")
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(INSERT_SUBREG (ExtendInfo.VT (IMPLICIT_DEF)),
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_.RC:$src, _.SubRegIdx)),
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_.KRC))>;
@@ -10499,14 +10499,14 @@ defm VPMOVQ2M : avx512_convert_vector_to_mask<0x39, "vpmovq2m",
1049910499
// a target independent DAG combine likes to combine sext and trunc.
1050010500
let Predicates = [HasDQI, NoBWI] in {
1050110501
def : Pat<(v16i8 (sext (v16i1 VK16:$src))),
10502-
(VPMOVDBZrr (v16i32 (VPMOVM2DZrr VK16:$src)))>;
10502+
(VPMOVDBZrr (v16i32 (VPMOVM2DZrk VK16:$src)))>;
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def : Pat<(v16i16 (sext (v16i1 VK16:$src))),
10504-
(VPMOVDWZrr (v16i32 (VPMOVM2DZrr VK16:$src)))>;
10504+
(VPMOVDWZrr (v16i32 (VPMOVM2DZrk VK16:$src)))>;
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}
1050610506

1050710507
let Predicates = [HasDQI, NoBWI, HasVLX] in {
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def : Pat<(v8i16 (sext (v8i1 VK8:$src))),
10509-
(VPMOVDWZ256rr (v8i32 (VPMOVM2DZ256rr VK8:$src)))>;
10509+
(VPMOVDWZ256rr (v8i32 (VPMOVM2DZ256rk VK8:$src)))>;
1051010510
}
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//===----------------------------------------------------------------------===//

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