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Merge remote-tracking branch 'origin/main' into vplan-simplify-branch-on-const-entry
2 parents 7b19cec + 82245fc commit c9228c1

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11 files changed

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‎llvm/test/Transforms/LoopVectorize/make-followup-loop-id.ll‎

Lines changed: 84 additions & 62 deletions
Original file line numberDiff line numberDiff line change
@@ -1,9 +1,9 @@
11
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
2-
; RUN: opt -passes='loop-vectorize,loop-unroll' -force-vector-width=4 -S < %s | FileCheck %s
2+
; RUN: opt -passes='loop-vectorize' -force-vector-width=4 -S < %s | FileCheck %s
33

44
; Test if the follow-up metadata for loops works fine. The original code is
5-
; something like below. In this case, unrolling should be applied after
6-
; vectorization.
5+
; something like below. In this case, the unrolling metadata from the original
6+
; loop should be applied to the vector loop as well.
77
;
88
; void f(float *a, float x) {
99
; #pragma clang loop vectorize(enable) unroll_count(8)
@@ -12,8 +12,8 @@
1212
; }
1313
; }
1414
;
15-
define void @f(ptr noundef captures(none) %a, float noundef %x) {
16-
; CHECK-LABEL: define void @f(
15+
define void @scalar_loop_dead(ptr noundef captures(none) %a, float noundef %x) {
16+
; CHECK-LABEL: define void @scalar_loop_dead(
1717
; CHECK-SAME: ptr noundef captures(none) [[A:%.*]], float noundef [[X:%.*]]) {
1818
; CHECK-NEXT: [[ENTRY:.*:]]
1919
; CHECK-NEXT: br label %[[VECTOR_PH:.*]]
@@ -22,93 +22,115 @@ define void @f(ptr noundef captures(none) %a, float noundef %x) {
2222
; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x float> [[BROADCAST_SPLATINSERT]], <4 x float> poison, <4 x i32> zeroinitializer
2323
; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
2424
; CHECK: [[VECTOR_BODY]]:
25-
; CHECK-NEXT: [[INDEX_NEXT_6:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
26-
; CHECK-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw float, ptr [[A]], i64 [[INDEX_NEXT_6]]
27-
; CHECK-NEXT: [[WIDE_LOAD_7:%.*]] = load <4 x float>, ptr [[TMP14]], align 4
28-
; CHECK-NEXT: [[TMP15:%.*]] = fmul <4 x float> [[BROADCAST_SPLAT]], [[WIDE_LOAD_7]]
29-
; CHECK-NEXT: store <4 x float> [[TMP15]], ptr [[TMP14]], align 4
30-
; CHECK-NEXT: [[INDEX_NEXT1:%.*]] = add nuw nsw i64 [[INDEX_NEXT_6]], 4
31-
; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw float, ptr [[A]], i64 [[INDEX_NEXT1]]
32-
; CHECK-NEXT: [[WIDE_LOAD_1:%.*]] = load <4 x float>, ptr [[TMP2]], align 4
33-
; CHECK-NEXT: [[TMP3:%.*]] = fmul <4 x float> [[BROADCAST_SPLAT]], [[WIDE_LOAD_1]]
34-
; CHECK-NEXT: store <4 x float> [[TMP3]], ptr [[TMP2]], align 4
35-
; CHECK-NEXT: [[INDEX_NEXT_1:%.*]] = add nuw nsw i64 [[INDEX_NEXT_6]], 8
36-
; CHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw float, ptr [[A]], i64 [[INDEX_NEXT_1]]
37-
; CHECK-NEXT: [[WIDE_LOAD_2:%.*]] = load <4 x float>, ptr [[TMP16]], align 4
38-
; CHECK-NEXT: [[TMP5:%.*]] = fmul <4 x float> [[BROADCAST_SPLAT]], [[WIDE_LOAD_2]]
39-
; CHECK-NEXT: store <4 x float> [[TMP5]], ptr [[TMP16]], align 4
40-
; CHECK-NEXT: [[INDEX_NEXT_2:%.*]] = add nuw nsw i64 [[INDEX_NEXT_6]], 12
41-
; CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw float, ptr [[A]], i64 [[INDEX_NEXT_2]]
42-
; CHECK-NEXT: [[WIDE_LOAD_3:%.*]] = load <4 x float>, ptr [[TMP6]], align 4
43-
; CHECK-NEXT: [[TMP7:%.*]] = fmul <4 x float> [[BROADCAST_SPLAT]], [[WIDE_LOAD_3]]
44-
; CHECK-NEXT: store <4 x float> [[TMP7]], ptr [[TMP6]], align 4
45-
; CHECK-NEXT: [[INDEX_NEXT_3:%.*]] = add nuw nsw i64 [[INDEX_NEXT_6]], 16
46-
; CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw float, ptr [[A]], i64 [[INDEX_NEXT_3]]
47-
; CHECK-NEXT: [[WIDE_LOAD_4:%.*]] = load <4 x float>, ptr [[TMP8]], align 4
48-
; CHECK-NEXT: [[TMP9:%.*]] = fmul <4 x float> [[BROADCAST_SPLAT]], [[WIDE_LOAD_4]]
49-
; CHECK-NEXT: store <4 x float> [[TMP9]], ptr [[TMP8]], align 4
50-
; CHECK-NEXT: [[INDEX_NEXT_4:%.*]] = add nuw nsw i64 [[INDEX_NEXT_6]], 20
51-
; CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw float, ptr [[A]], i64 [[INDEX_NEXT_4]]
52-
; CHECK-NEXT: [[WIDE_LOAD_5:%.*]] = load <4 x float>, ptr [[TMP10]], align 4
53-
; CHECK-NEXT: [[TMP11:%.*]] = fmul <4 x float> [[BROADCAST_SPLAT]], [[WIDE_LOAD_5]]
54-
; CHECK-NEXT: store <4 x float> [[TMP11]], ptr [[TMP10]], align 4
55-
; CHECK-NEXT: [[INDEX_NEXT_5:%.*]] = add nuw nsw i64 [[INDEX_NEXT_6]], 24
56-
; CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw float, ptr [[A]], i64 [[INDEX_NEXT_5]]
57-
; CHECK-NEXT: [[WIDE_LOAD_6:%.*]] = load <4 x float>, ptr [[TMP12]], align 4
58-
; CHECK-NEXT: [[TMP13:%.*]] = fmul <4 x float> [[BROADCAST_SPLAT]], [[WIDE_LOAD_6]]
59-
; CHECK-NEXT: store <4 x float> [[TMP13]], ptr [[TMP12]], align 4
60-
; CHECK-NEXT: [[INDEX_NEXT_7:%.*]] = add nuw nsw i64 [[INDEX_NEXT_6]], 28
61-
; CHECK-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw float, ptr [[A]], i64 [[INDEX_NEXT_7]]
62-
; CHECK-NEXT: [[WIDE_LOAD_8:%.*]] = load <4 x float>, ptr [[TMP17]], align 4
63-
; CHECK-NEXT: [[TMP18:%.*]] = fmul <4 x float> [[BROADCAST_SPLAT]], [[WIDE_LOAD_8]]
64-
; CHECK-NEXT: store <4 x float> [[TMP18]], ptr [[TMP17]], align 4
65-
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw nsw i64 [[INDEX_NEXT_6]], 32
66-
; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1024
67-
; CHECK-NEXT: br i1 [[TMP4]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
25+
; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
26+
; CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw float, ptr [[A]], i64 [[INDEX]]
27+
; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x float>, ptr [[TMP0]], align 4
28+
; CHECK-NEXT: [[TMP1:%.*]] = fmul <4 x float> [[BROADCAST_SPLAT]], [[WIDE_LOAD]]
29+
; CHECK-NEXT: store <4 x float> [[TMP1]], ptr [[TMP0]], align 4
30+
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
31+
; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1024
32+
; CHECK-NEXT: br i1 [[TMP2]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
6833
; CHECK: [[MIDDLE_BLOCK]]:
6934
; CHECK-NEXT: br label %[[EXIT:.*]]
7035
; CHECK: [[SCALAR_PH:.*]]:
71-
; CHECK-NEXT: br label %[[FOR_BODY:.*]]
72-
; CHECK: [[FOR_BODY]]:
73-
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[FOR_BODY]] ]
36+
; CHECK-NEXT: br label %[[LOOP:.*]]
37+
; CHECK: [[LOOP]]:
38+
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
7439
; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds nuw float, ptr [[A]], i64 [[IV]]
7540
; CHECK-NEXT: [[LOAD:%.*]] = load float, ptr [[ARRAYIDX]], align 4
7641
; CHECK-NEXT: [[MUL:%.*]] = fmul float [[X]], [[LOAD]]
7742
; CHECK-NEXT: store float [[MUL]], ptr [[ARRAYIDX]], align 4
7843
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
7944
; CHECK-NEXT: [[COMP:%.*]] = icmp eq i64 [[IV_NEXT]], 1024
80-
; CHECK-NEXT: br i1 [[COMP]], label %[[EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]]
45+
; CHECK-NEXT: br i1 [[COMP]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP4:![0-9]+]]
8146
; CHECK: [[EXIT]]:
8247
; CHECK-NEXT: ret void
8348
;
8449
entry:
85-
br label %for.body
50+
br label %loop
8651

87-
for.body:
88-
%iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
52+
loop:
53+
%iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
8954
%arrayidx = getelementptr inbounds nuw float, ptr %a, i64 %iv
9055
%load = load float, ptr %arrayidx, align 4
9156
%mul = fmul float %x, %load
9257
store float %mul, ptr %arrayidx, align 4
9358
%iv.next = add nuw nsw i64 %iv, 1
9459
%comp = icmp eq i64 %iv.next, 1024
95-
br i1 %comp, label %exit, label %for.body, !llvm.loop !0
60+
br i1 %comp, label %exit, label %loop, !llvm.loop !0
9661

9762
exit:
9863
ret void
9964
}
10065

66+
define void @scalar_loop_live(ptr noundef captures(none) %a, float noundef %x, i64 %n) {
67+
; CHECK-LABEL: define void @scalar_loop_live(
68+
; CHECK-SAME: ptr noundef captures(none) [[A:%.*]], float noundef [[X:%.*]], i64 [[N:%.*]]) {
69+
; CHECK-NEXT: [[ENTRY:.*]]:
70+
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 4
71+
; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
72+
; CHECK: [[VECTOR_PH]]:
73+
; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N]], 4
74+
; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]]
75+
; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x float> poison, float [[X]], i64 0
76+
; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x float> [[BROADCAST_SPLATINSERT]], <4 x float> poison, <4 x i32> zeroinitializer
77+
; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
78+
; CHECK: [[VECTOR_BODY]]:
79+
; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
80+
; CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw float, ptr [[A]], i64 [[INDEX]]
81+
; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x float>, ptr [[TMP0]], align 4
82+
; CHECK-NEXT: [[TMP1:%.*]] = fmul <4 x float> [[BROADCAST_SPLAT]], [[WIDE_LOAD]]
83+
; CHECK-NEXT: store <4 x float> [[TMP1]], ptr [[TMP0]], align 4
84+
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
85+
; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
86+
; CHECK-NEXT: br i1 [[TMP2]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP7:![0-9]+]]
87+
; CHECK: [[MIDDLE_BLOCK]]:
88+
; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]]
89+
; CHECK-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]
90+
; CHECK: [[SCALAR_PH]]:
91+
; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
92+
; CHECK-NEXT: br label %[[LOOP:.*]]
93+
; CHECK: [[LOOP]]:
94+
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
95+
; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds nuw float, ptr [[A]], i64 [[IV]]
96+
; CHECK-NEXT: [[LOAD:%.*]] = load float, ptr [[ARRAYIDX]], align 4
97+
; CHECK-NEXT: [[MUL:%.*]] = fmul float [[X]], [[LOAD]]
98+
; CHECK-NEXT: store float [[MUL]], ptr [[ARRAYIDX]], align 4
99+
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
100+
; CHECK-NEXT: [[COMP:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]
101+
; CHECK-NEXT: br i1 [[COMP]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP8:![0-9]+]]
102+
; CHECK: [[EXIT]]:
103+
; CHECK-NEXT: ret void
104+
;
105+
entry:
106+
br label %loop
107+
108+
loop:
109+
%iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
110+
%arrayidx = getelementptr inbounds nuw float, ptr %a, i64 %iv
111+
%load = load float, ptr %arrayidx, align 4
112+
%mul = fmul float %x, %load
113+
store float %mul, ptr %arrayidx, align 4
114+
%iv.next = add nuw nsw i64 %iv, 1
115+
%comp = icmp eq i64 %iv.next, %n
116+
br i1 %comp, label %exit, label %loop, !llvm.loop !0
117+
118+
exit:
119+
ret void
120+
}
101121
!0 = distinct !{!0, !1, !2}
102122
!1 = !{!"llvm.loop.vectorize.enable", i1 true}
103123
!2 = !{!"llvm.loop.vectorize.followup_all", !3, !4}
104124
!3 = !{!"llvm.loop.isvectorized"}
105125
!4 = !{!"llvm.loop.unroll.count", i32 8}
106126
;.
107-
; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}
127+
; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]], [[META3:![0-9]+]]}
108128
; CHECK: [[META1]] = !{!"llvm.loop.isvectorized"}
109-
; CHECK: [[META2]] = !{!"llvm.loop.unroll.disable"}
110-
; CHECK: [[LOOP3]] = distinct !{[[LOOP3]], [[META4:![0-9]+]], [[META5:![0-9]+]]}
111-
; CHECK: [[META4]] = !{!"llvm.loop.vectorize.enable", i1 true}
112-
; CHECK: [[META5]] = !{!"llvm.loop.vectorize.followup_all", [[META1]], [[META6:![0-9]+]]}
113-
; CHECK: [[META6]] = !{!"llvm.loop.unroll.count", i32 8}
129+
; CHECK: [[META2]] = !{!"llvm.loop.unroll.count", i32 8}
130+
; CHECK: [[META3]] = !{!"llvm.loop.unroll.runtime.disable"}
131+
; CHECK: [[LOOP4]] = distinct !{[[LOOP4]], [[META5:![0-9]+]], [[META6:![0-9]+]]}
132+
; CHECK: [[META5]] = !{!"llvm.loop.vectorize.enable", i1 true}
133+
; CHECK: [[META6]] = !{!"llvm.loop.vectorize.followup_all", [[META1]], [[META2]]}
134+
; CHECK: [[LOOP7]] = distinct !{[[LOOP7]], [[META1]], [[META2]], [[META3]]}
135+
; CHECK: [[LOOP8]] = distinct !{[[LOOP8]], [[META1]], [[META2]]}
114136
;.

‎mlir/include/mlir/Dialect/Ptr/IR/MemorySpaceInterfaces.h‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -20,8 +20,8 @@
2020
namespace mlir {
2121
class Operation;
2222
namespace ptr {
23-
enum class AtomicBinOp : uint64_t;
24-
enum class AtomicOrdering : uint64_t;
23+
enum class AtomicBinOp : uint32_t;
24+
enum class AtomicOrdering : uint32_t;
2525
} // namespace ptr
2626
} // namespace mlir
2727

‎mlir/include/mlir/Dialect/Ptr/IR/MemorySpaceInterfaces.td‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -42,7 +42,7 @@ def MemorySpaceAttrInterface : AttrInterface<"MemorySpaceAttrInterface"> {
4242
/*methodName=*/ "isValidLoad",
4343
/*args=*/ (ins "::mlir::Type":$type,
4444
"::mlir::ptr::AtomicOrdering":$ordering,
45-
"::mlir::IntegerAttr":$alignment,
45+
"std::optional<int64_t>":$alignment,
4646
"::llvm::function_ref<::mlir::InFlightDiagnostic()>":$emitError)
4747
>,
4848
InterfaceMethod<
@@ -57,7 +57,7 @@ def MemorySpaceAttrInterface : AttrInterface<"MemorySpaceAttrInterface"> {
5757
/*methodName=*/ "isValidStore",
5858
/*args=*/ (ins "::mlir::Type":$type,
5959
"::mlir::ptr::AtomicOrdering":$ordering,
60-
"::mlir::IntegerAttr":$alignment,
60+
"std::optional<int64_t>":$alignment,
6161
"::llvm::function_ref<::mlir::InFlightDiagnostic()>":$emitError)
6262
>,
6363
InterfaceMethod<
@@ -73,7 +73,7 @@ def MemorySpaceAttrInterface : AttrInterface<"MemorySpaceAttrInterface"> {
7373
/*args=*/ (ins "::mlir::ptr::AtomicBinOp":$op,
7474
"::mlir::Type":$type,
7575
"::mlir::ptr::AtomicOrdering":$ordering,
76-
"::mlir::IntegerAttr":$alignment,
76+
"std::optional<int64_t>":$alignment,
7777
"::llvm::function_ref<::mlir::InFlightDiagnostic()>":$emitError)
7878
>,
7979
InterfaceMethod<
@@ -90,7 +90,7 @@ def MemorySpaceAttrInterface : AttrInterface<"MemorySpaceAttrInterface"> {
9090
/*args=*/ (ins "::mlir::Type":$type,
9191
"::mlir::ptr::AtomicOrdering":$successOrdering,
9292
"::mlir::ptr::AtomicOrdering":$failureOrdering,
93-
"::mlir::IntegerAttr":$alignment,
93+
"std::optional<int64_t>":$alignment,
9494
"::llvm::function_ref<::mlir::InFlightDiagnostic()>":$emitError)
9595
>,
9696
InterfaceMethod<

‎mlir/include/mlir/Dialect/Ptr/IR/PtrEnums.td‎

Lines changed: 28 additions & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -15,25 +15,25 @@ include "mlir/IR/EnumAttr.td"
1515
// Atomic binary op enum attribute.
1616
//===----------------------------------------------------------------------===//
1717

18-
def AtomicBinOpXchg : I64EnumAttrCase<"xchg", 0, "xchg">;
19-
def AtomicBinOpAdd : I64EnumAttrCase<"add", 1, "add">;
20-
def AtomicBinOpSub : I64EnumAttrCase<"sub", 2, "sub">;
21-
def AtomicBinOpAnd : I64EnumAttrCase<"_and", 3, "_and">;
22-
def AtomicBinOpNand : I64EnumAttrCase<"nand", 4, "nand">;
23-
def AtomicBinOpOr : I64EnumAttrCase<"_or", 5, "_or">;
24-
def AtomicBinOpXor : I64EnumAttrCase<"_xor", 6, "_xor">;
25-
def AtomicBinOpMax : I64EnumAttrCase<"max", 7, "max">;
26-
def AtomicBinOpMin : I64EnumAttrCase<"min", 8, "min">;
27-
def AtomicBinOpUMax : I64EnumAttrCase<"umax", 9, "umax">;
28-
def AtomicBinOpUMin : I64EnumAttrCase<"umin", 10, "umin">;
29-
def AtomicBinOpFAdd : I64EnumAttrCase<"fadd", 11, "fadd">;
30-
def AtomicBinOpFSub : I64EnumAttrCase<"fsub", 12, "fsub">;
31-
def AtomicBinOpFMax : I64EnumAttrCase<"fmax", 13, "fmax">;
32-
def AtomicBinOpFMin : I64EnumAttrCase<"fmin", 14, "fmin">;
33-
def AtomicBinOpUIncWrap : I64EnumAttrCase<"uinc_wrap", 15, "uinc_wrap">;
34-
def AtomicBinOpUDecWrap : I64EnumAttrCase<"udec_wrap", 16, "udec_wrap">;
18+
def AtomicBinOpXchg : I32EnumCase<"xchg", 0, "xchg">;
19+
def AtomicBinOpAdd : I32EnumCase<"add", 1, "add">;
20+
def AtomicBinOpSub : I32EnumCase<"sub", 2, "sub">;
21+
def AtomicBinOpAnd : I32EnumCase<"_and", 3, "_and">;
22+
def AtomicBinOpNand : I32EnumCase<"nand", 4, "nand">;
23+
def AtomicBinOpOr : I32EnumCase<"_or", 5, "_or">;
24+
def AtomicBinOpXor : I32EnumCase<"_xor", 6, "_xor">;
25+
def AtomicBinOpMax : I32EnumCase<"max", 7, "max">;
26+
def AtomicBinOpMin : I32EnumCase<"min", 8, "min">;
27+
def AtomicBinOpUMax : I32EnumCase<"umax", 9, "umax">;
28+
def AtomicBinOpUMin : I32EnumCase<"umin", 10, "umin">;
29+
def AtomicBinOpFAdd : I32EnumCase<"fadd", 11, "fadd">;
30+
def AtomicBinOpFSub : I32EnumCase<"fsub", 12, "fsub">;
31+
def AtomicBinOpFMax : I32EnumCase<"fmax", 13, "fmax">;
32+
def AtomicBinOpFMin : I32EnumCase<"fmin", 14, "fmin">;
33+
def AtomicBinOpUIncWrap : I32EnumCase<"uinc_wrap", 15, "uinc_wrap">;
34+
def AtomicBinOpUDecWrap : I32EnumCase<"udec_wrap", 16, "udec_wrap">;
3535

36-
def AtomicBinOp : I64EnumAttr<
36+
def AtomicBinOp : I32Enum<
3737
"AtomicBinOp",
3838
"ptr.atomicrmw binary operations",
3939
[AtomicBinOpXchg, AtomicBinOpAdd, AtomicBinOpSub, AtomicBinOpAnd,
@@ -48,15 +48,15 @@ def AtomicBinOp : I64EnumAttr<
4848
// Atomic ordering enum attribute.
4949
//===----------------------------------------------------------------------===//
5050

51-
def AtomicOrderingNotAtomic : I64EnumAttrCase<"not_atomic", 0, "not_atomic">;
52-
def AtomicOrderingUnordered : I64EnumAttrCase<"unordered", 1, "unordered">;
53-
def AtomicOrderingMonotonic : I64EnumAttrCase<"monotonic", 2, "monotonic">;
54-
def AtomicOrderingAcquire : I64EnumAttrCase<"acquire", 3, "acquire">;
55-
def AtomicOrderingRelease : I64EnumAttrCase<"release", 4, "release">;
56-
def AtomicOrderingAcqRel : I64EnumAttrCase<"acq_rel", 5, "acq_rel">;
57-
def AtomicOrderingSeqCst : I64EnumAttrCase<"seq_cst", 6, "seq_cst">;
51+
def AtomicOrderingNotAtomic : I32EnumCase<"not_atomic", 0, "not_atomic">;
52+
def AtomicOrderingUnordered : I32EnumCase<"unordered", 1, "unordered">;
53+
def AtomicOrderingMonotonic : I32EnumCase<"monotonic", 2, "monotonic">;
54+
def AtomicOrderingAcquire : I32EnumCase<"acquire", 3, "acquire">;
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def AtomicOrderingRelease : I32EnumCase<"release", 4, "release">;
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def AtomicOrderingAcqRel : I32EnumCase<"acq_rel", 5, "acq_rel">;
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def AtomicOrderingSeqCst : I32EnumCase<"seq_cst", 6, "seq_cst">;
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59-
def AtomicOrdering : I64EnumAttr<
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def AtomicOrdering : I32Enum<
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"AtomicOrdering",
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"Atomic ordering for LLVM's memory model",
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[AtomicOrderingNotAtomic, AtomicOrderingUnordered, AtomicOrderingMonotonic,
@@ -66,6 +66,8 @@ def AtomicOrdering : I64EnumAttr<
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let cppNamespace = "::mlir::ptr";
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}
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def AtomicOrderingProp : EnumProp<AtomicOrdering>;
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//===----------------------------------------------------------------------===//
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// Ptr add flags enum properties.
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//===----------------------------------------------------------------------===//

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