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[RISCV] remove umax in trunc-sat-clip-sdnode.ll and fixed-vectors-trunc-sat-clip.ll.
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2 files changed

+30
-48
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2 files changed

+30
-48
lines changed

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-trunc-sat-clip.ll

Lines changed: 15 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -8,11 +8,8 @@ declare <4 x i32> @llvm.smin.v4i32(<4 x i32>, <4 x i32>)
88
declare <4 x i64> @llvm.smax.v4i64(<4 x i64>, <4 x i64>)
99
declare <4 x i64> @llvm.smin.v4i64(<4 x i64>, <4 x i64>)
1010

11-
declare <4 x i16> @llvm.umax.v4i16(<4 x i16>, <4 x i16>)
1211
declare <4 x i16> @llvm.umin.v4i16(<4 x i16>, <4 x i16>)
13-
declare <4 x i32> @llvm.umax.v4i32(<4 x i32>, <4 x i32>)
1412
declare <4 x i32> @llvm.umin.v4i32(<4 x i32>, <4 x i32>)
15-
declare <4 x i64> @llvm.umax.v4i64(<4 x i64>, <4 x i64>)
1613
declare <4 x i64> @llvm.umin.v4i64(<4 x i64>, <4 x i64>)
1714

1815
define void @trunc_sat_i8i16_maxmin(ptr %x, ptr %y) {
@@ -110,10 +107,9 @@ define void @trunc_sat_u8u16_maxmin(ptr %x, ptr %y) {
110107
; CHECK-NEXT: vse8.v v8, (a1)
111108
; CHECK-NEXT: ret
112109
%1 = load <4 x i16>, ptr %x, align 16
113-
%2 = tail call <4 x i16> @llvm.umax.v4i16(<4 x i16> %1, <4 x i16> <i16 0, i16 0, i16 0, i16 0>)
114-
%3 = tail call <4 x i16> @llvm.umin.v4i16(<4 x i16> %2, <4 x i16> <i16 255, i16 255, i16 255, i16 255>)
115-
%4 = trunc <4 x i16> %3 to <4 x i8>
116-
store <4 x i8> %4, ptr %y, align 8
110+
%2 = tail call <4 x i16> @llvm.umin.v4i16(<4 x i16> %1, <4 x i16> <i16 255, i16 255, i16 255, i16 255>)
111+
%3 = trunc <4 x i16> %2 to <4 x i8>
112+
store <4 x i8> %3, ptr %y, align 8
117113
ret void
118114
}
119115

@@ -127,9 +123,8 @@ define void @trunc_sat_u8u16_minmax(ptr %x, ptr %y) {
127123
; CHECK-NEXT: ret
128124
%1 = load <4 x i16>, ptr %x, align 16
129125
%2 = tail call <4 x i16> @llvm.umin.v4i16(<4 x i16> %1, <4 x i16> <i16 255, i16 255, i16 255, i16 255>)
130-
%3 = tail call <4 x i16> @llvm.umax.v4i16(<4 x i16> %2, <4 x i16> <i16 0, i16 0, i16 0, i16 0>)
131-
%4 = trunc <4 x i16> %3 to <4 x i8>
132-
store <4 x i8> %4, ptr %y, align 8
126+
%3 = trunc <4 x i16> %2 to <4 x i8>
127+
store <4 x i8> %3, ptr %y, align 8
133128
ret void
134129
}
135130

@@ -231,10 +226,9 @@ define void @trunc_sat_u16u32_minmax(ptr %x, ptr %y) {
231226
; CHECK-NEXT: vse16.v v8, (a1)
232227
; CHECK-NEXT: ret
233228
%1 = load <4 x i32>, ptr %x, align 32
234-
%2 = tail call <4 x i32> @llvm.umax.v4i32(<4 x i32> %1, <4 x i32> <i32 0, i32 0, i32 0, i32 0>)
235-
%3 = tail call <4 x i32> @llvm.umin.v4i32(<4 x i32> %2, <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535>)
236-
%4 = trunc <4 x i32> %3 to <4 x i16>
237-
store <4 x i16> %4, ptr %y, align 16
229+
%2 = tail call <4 x i32> @llvm.umin.v4i32(<4 x i32> %1, <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535>)
230+
%3 = trunc <4 x i32> %2 to <4 x i16>
231+
store <4 x i16> %3, ptr %y, align 16
238232
ret void
239233
}
240234

@@ -248,9 +242,8 @@ define void @trunc_sat_u16u32_maxmin(ptr %x, ptr %y) {
248242
; CHECK-NEXT: ret
249243
%1 = load <4 x i32>, ptr %x, align 32
250244
%2 = tail call <4 x i32> @llvm.umin.v4i32(<4 x i32> %1, <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535>)
251-
%3 = tail call <4 x i32> @llvm.umax.v4i32(<4 x i32> %2, <4 x i32> <i32 0, i32 0, i32 0, i32 0>)
252-
%4 = trunc <4 x i32> %3 to <4 x i16>
253-
store <4 x i16> %4, ptr %y, align 16
245+
%3 = trunc <4 x i32> %2 to <4 x i16>
246+
store <4 x i16> %3, ptr %y, align 16
254247
ret void
255248
}
256249

@@ -355,10 +348,9 @@ define void @trunc_sat_u32u64_maxmin(ptr %x, ptr %y) {
355348
; CHECK-NEXT: vse32.v v10, (a1)
356349
; CHECK-NEXT: ret
357350
%1 = load <4 x i64>, ptr %x, align 64
358-
%2 = tail call <4 x i64> @llvm.umax.v4i64(<4 x i64> %1, <4 x i64> <i64 0, i64 0, i64 0, i64 0>)
359-
%3 = tail call <4 x i64> @llvm.umin.v4i64(<4 x i64> %2, <4 x i64> <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295>)
360-
%4 = trunc <4 x i64> %3 to <4 x i32>
361-
store <4 x i32> %4, ptr %y, align 32
351+
%2 = tail call <4 x i64> @llvm.umin.v4i64(<4 x i64> %1, <4 x i64> <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295>)
352+
%3 = trunc <4 x i64> %2 to <4 x i32>
353+
store <4 x i32> %3, ptr %y, align 32
362354
ret void
363355
}
364356

@@ -372,8 +364,7 @@ define void @trunc_sat_u32u64_minmax(ptr %x, ptr %y) {
372364
; CHECK-NEXT: ret
373365
%1 = load <4 x i64>, ptr %x, align 64
374366
%2 = tail call <4 x i64> @llvm.umin.v4i64(<4 x i64> %1, <4 x i64> <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295>)
375-
%3 = tail call <4 x i64> @llvm.umax.v4i64(<4 x i64> %2, <4 x i64> <i64 0, i64 0, i64 0, i64 0>)
376-
%4 = trunc <4 x i64> %3 to <4 x i32>
377-
store <4 x i32> %4, ptr %y, align 32
367+
%3 = trunc <4 x i64> %2 to <4 x i32>
368+
store <4 x i32> %3, ptr %y, align 32
378369
ret void
379370
}

llvm/test/CodeGen/RISCV/rvv/trunc-sat-clip-sdnode.ll

Lines changed: 15 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -8,11 +8,8 @@ declare <vscale x 4 x i32> @llvm.smin.v4i32(<vscale x 4 x i32>, <vscale x 4 x i3
88
declare <vscale x 4 x i64> @llvm.smax.v4i64(<vscale x 4 x i64>, <vscale x 4 x i64>)
99
declare <vscale x 4 x i64> @llvm.smin.v4i64(<vscale x 4 x i64>, <vscale x 4 x i64>)
1010

11-
declare <vscale x 4 x i16> @llvm.umax.v4i16(<vscale x 4 x i16>, <vscale x 4 x i16>)
1211
declare <vscale x 4 x i16> @llvm.umin.v4i16(<vscale x 4 x i16>, <vscale x 4 x i16>)
13-
declare <vscale x 4 x i32> @llvm.umax.v4i32(<vscale x 4 x i32>, <vscale x 4 x i32>)
1412
declare <vscale x 4 x i32> @llvm.umin.v4i32(<vscale x 4 x i32>, <vscale x 4 x i32>)
15-
declare <vscale x 4 x i64> @llvm.umax.v4i64(<vscale x 4 x i64>, <vscale x 4 x i64>)
1613
declare <vscale x 4 x i64> @llvm.umin.v4i64(<vscale x 4 x i64>, <vscale x 4 x i64>)
1714

1815
define void @trunc_sat_i8i16_maxmin(ptr %x, ptr %y) {
@@ -110,10 +107,9 @@ define void @trunc_sat_u8u16_maxmin(ptr %x, ptr %y) {
110107
; CHECK-NEXT: vse8.v v8, (a1)
111108
; CHECK-NEXT: ret
112109
%1 = load <vscale x 4 x i16>, ptr %x, align 16
113-
%2 = tail call <vscale x 4 x i16> @llvm.umax.v4i16(<vscale x 4 x i16> %1, <vscale x 4 x i16> splat (i16 0))
114-
%3 = tail call <vscale x 4 x i16> @llvm.umin.v4i16(<vscale x 4 x i16> %2, <vscale x 4 x i16> splat (i16 255))
115-
%4 = trunc <vscale x 4 x i16> %3 to <vscale x 4 x i8>
116-
store <vscale x 4 x i8> %4, ptr %y, align 8
110+
%2 = tail call <vscale x 4 x i16> @llvm.umin.v4i16(<vscale x 4 x i16> %1, <vscale x 4 x i16> splat (i16 255))
111+
%3 = trunc <vscale x 4 x i16> %2 to <vscale x 4 x i8>
112+
store <vscale x 4 x i8> %3, ptr %y, align 8
117113
ret void
118114
}
119115

@@ -127,9 +123,8 @@ define void @trunc_sat_u8u16_minmax(ptr %x, ptr %y) {
127123
; CHECK-NEXT: ret
128124
%1 = load <vscale x 4 x i16>, ptr %x, align 16
129125
%2 = tail call <vscale x 4 x i16> @llvm.umin.v4i16(<vscale x 4 x i16> %1, <vscale x 4 x i16> splat (i16 255))
130-
%3 = tail call <vscale x 4 x i16> @llvm.umax.v4i16(<vscale x 4 x i16> %2, <vscale x 4 x i16> splat (i16 0))
131-
%4 = trunc <vscale x 4 x i16> %3 to <vscale x 4 x i8>
132-
store <vscale x 4 x i8> %4, ptr %y, align 8
126+
%3 = trunc <vscale x 4 x i16> %2 to <vscale x 4 x i8>
127+
store <vscale x 4 x i8> %3, ptr %y, align 8
133128
ret void
134129
}
135130

@@ -231,10 +226,9 @@ define void @trunc_sat_u16u32_minmax(ptr %x, ptr %y) {
231226
; CHECK-NEXT: vs1r.v v10, (a1)
232227
; CHECK-NEXT: ret
233228
%1 = load <vscale x 4 x i32>, ptr %x, align 32
234-
%2 = tail call <vscale x 4 x i32> @llvm.umax.v4i32(<vscale x 4 x i32> %1, <vscale x 4 x i32> splat (i32 0))
235-
%3 = tail call <vscale x 4 x i32> @llvm.umin.v4i32(<vscale x 4 x i32> %2, <vscale x 4 x i32> splat (i32 65535))
236-
%4 = trunc <vscale x 4 x i32> %3 to <vscale x 4 x i16>
237-
store <vscale x 4 x i16> %4, ptr %y, align 16
229+
%2 = tail call <vscale x 4 x i32> @llvm.umin.v4i32(<vscale x 4 x i32> %1, <vscale x 4 x i32> splat (i32 65535))
230+
%3 = trunc <vscale x 4 x i32> %2 to <vscale x 4 x i16>
231+
store <vscale x 4 x i16> %3, ptr %y, align 16
238232
ret void
239233
}
240234

@@ -248,9 +242,8 @@ define void @trunc_sat_u16u32_maxmin(ptr %x, ptr %y) {
248242
; CHECK-NEXT: ret
249243
%1 = load <vscale x 4 x i32>, ptr %x, align 32
250244
%2 = tail call <vscale x 4 x i32> @llvm.umin.v4i32(<vscale x 4 x i32> %1, <vscale x 4 x i32> splat (i32 65535))
251-
%3 = tail call <vscale x 4 x i32> @llvm.umax.v4i32(<vscale x 4 x i32> %2, <vscale x 4 x i32> splat (i32 0))
252-
%4 = trunc <vscale x 4 x i32> %3 to <vscale x 4 x i16>
253-
store <vscale x 4 x i16> %4, ptr %y, align 16
245+
%3 = trunc <vscale x 4 x i32> %2 to <vscale x 4 x i16>
246+
store <vscale x 4 x i16> %3, ptr %y, align 16
254247
ret void
255248
}
256249

@@ -355,10 +348,9 @@ define void @trunc_sat_u32u64_maxmin(ptr %x, ptr %y) {
355348
; CHECK-NEXT: vs2r.v v12, (a1)
356349
; CHECK-NEXT: ret
357350
%1 = load <vscale x 4 x i64>, ptr %x, align 64
358-
%2 = tail call <vscale x 4 x i64> @llvm.umax.v4i64(<vscale x 4 x i64> %1, <vscale x 4 x i64> splat (i64 0))
359-
%3 = tail call <vscale x 4 x i64> @llvm.umin.v4i64(<vscale x 4 x i64> %2, <vscale x 4 x i64> splat (i64 4294967295))
360-
%4 = trunc <vscale x 4 x i64> %3 to <vscale x 4 x i32>
361-
store <vscale x 4 x i32> %4, ptr %y, align 32
351+
%2 = tail call <vscale x 4 x i64> @llvm.umin.v4i64(<vscale x 4 x i64> %1, <vscale x 4 x i64> splat (i64 4294967295))
352+
%3 = trunc <vscale x 4 x i64> %2 to <vscale x 4 x i32>
353+
store <vscale x 4 x i32> %3, ptr %y, align 32
362354
ret void
363355
}
364356

@@ -372,8 +364,7 @@ define void @trunc_sat_u32u64_minmax(ptr %x, ptr %y) {
372364
; CHECK-NEXT: ret
373365
%1 = load <vscale x 4 x i64>, ptr %x, align 64
374366
%2 = tail call <vscale x 4 x i64> @llvm.umin.v4i64(<vscale x 4 x i64> %1, <vscale x 4 x i64> splat (i64 4294967295))
375-
%3 = tail call <vscale x 4 x i64> @llvm.umax.v4i64(<vscale x 4 x i64> %2, <vscale x 4 x i64> splat (i64 0))
376-
%4 = trunc <vscale x 4 x i64> %3 to <vscale x 4 x i32>
377-
store <vscale x 4 x i32> %4, ptr %y, align 32
367+
%3 = trunc <vscale x 4 x i64> %2 to <vscale x 4 x i32>
368+
store <vscale x 4 x i32> %3, ptr %y, align 32
378369
ret void
379370
}

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