check canReplaceReg

Author: Pierre-vh

llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h

@@ -995,7 +995,8 @@ class CombinerHelper {
   bool matchSuboCarryOut(const MachineInstr &MI, BuildFnTy &MatchInfo) const;
 
   // (sext_inreg (sext_inreg x, K0), K1)
-  void applyRedundantSextInReg(MachineInstr &Root, MachineInstr &Other) const;
+  bool matchRedundantSextInReg(MachineInstr &Root, MachineInstr &Other,
+                               BuildFnTy &MatchInfo) const;
 
 private:
   /// Checks for legality of an indexed variant of \p LdSt.

llvm/include/llvm/Target/GlobalISel/Combine.td

@@ -1850,10 +1850,11 @@ def anyext_of_zext : ext_of_ext_opcodes<G_ANYEXT, G_ZEXT>;
 def anyext_of_sext : ext_of_ext_opcodes<G_ANYEXT, G_SEXT>;
 
 def sext_inreg_of_sext_inreg : GICombineRule<
-   (defs root:$dst),
+   (defs root:$dst, build_fn_matchinfo:$matchinfo),
    (match (G_SEXT_INREG $x, $src, $a):$other,
-          (G_SEXT_INREG $dst, $x, $b):$root),
-   (apply [{ Helper.applyRedundantSextInReg(*${root}, *${other}); }])>;
+          (G_SEXT_INREG $dst, $x, $b):$root,
+          [{ return Helper.matchRedundantSextInReg(*${root}, *${other}, ${matchinfo}); }]),
+   (apply [{ Helper.applyBuildFn(*${root}, ${matchinfo}); }])>;
 
 // Push cast through build vector.
 class buildvector_of_opcode<Instruction castOpcode> : GICombineRule <

llvm/lib/CodeGen/GlobalISel/CombinerHelperCasts.cpp

@@ -379,8 +379,9 @@ bool CombinerHelper::matchCastOfInteger(const MachineInstr &CastMI,
   }
 }
 
-void CombinerHelper::applyRedundantSextInReg(MachineInstr &Root,
-                                             MachineInstr &Other) const {
+bool CombinerHelper::matchRedundantSextInReg(MachineInstr &Root,
+                                             MachineInstr &Other,
+                                             BuildFnTy &MatchInfo) const {
   assert(Root.getOpcode() == TargetOpcode::G_SEXT_INREG &&
          Other.getOpcode() == TargetOpcode::G_SEXT_INREG);
 
@@ -394,14 +395,19 @@ void CombinerHelper::applyRedundantSextInReg(MachineInstr &Root,
   if (RootWidth >= OtherWidth) {
     // The root sext_inreg is entirely redundant because the other one
     // is narrower.
-    Observer.changingAllUsesOfReg(MRI, Dst);
-    MRI.replaceRegWith(Dst, OtherDst);
-    Observer.finishedChangingAllUsesOfReg();
+    if (!canReplaceReg(Dst, OtherDst, MRI))
+      return false;
+
+    MatchInfo = [=](MachineIRBuilder &B) {
+      Observer.changingAllUsesOfReg(MRI, Dst);
+      MRI.replaceRegWith(Dst, OtherDst);
+      Observer.finishedChangingAllUsesOfReg();
+    };
   } else {
     // RootWidth < OtherWidth, rewrite this G_SEXT_INREG with the source of the
     // other G_SEXT_INREG.
-    Builder.buildSExtInReg(Dst, Src, RootWidth);
+    MatchInfo = [=](MachineIRBuilder &B) {
+      B.buildSExtInReg(Dst, Src, RootWidth);
+    };
   }
-
-  Root.eraseFromParent();
 }