@@ -881,6 +881,9 @@ NVPTXTargetLowering::NVPTXTargetLowering(const NVPTXTargetMachine &TM,
881881 // i32 = truncate (i64 = srl (i64 = build_pair (X, Y), 32))
882882 // -> i32 Y
883883 setTargetDAGCombine (ISD::TRUNCATE);
884+ // i64 = build_pair ({i32, i32} = CopyFromReg (CopyToReg (i64 X)))
885+ // -> i64 X
886+ setTargetDAGCombine (ISD::BUILD_PAIR);
884887 }
885888
886889 // These map to conversion instructions for scalar FP types.
@@ -5322,6 +5325,31 @@ static SDValue PerformTRUNCATECombine(SDNode *N,
53225325 return SDValue ();
53235326}
53245327
5328+ static SDValue PerformBUILD_PAIRCombine (SDNode *N,
5329+ TargetLowering::DAGCombinerInfo &DCI,
5330+ CodeGenOptLevel OptLevel) {
5331+ if (OptLevel == CodeGenOptLevel::None)
5332+ return SDValue ();
5333+
5334+ EVT ToVT = N->getValueType (0 );
5335+ SDValue Op0 = N->getOperand (0 );
5336+ SDValue Op1 = N->getOperand (1 );
5337+ // i64 = build_pair ({i32, i32} = CopyFromReg (CopyToReg (i64 X)))
5338+ // -> i64 X
5339+ if (ToVT == MVT::i64 && Op0.getOpcode () == ISD::CopyFromReg &&
5340+ Op1.getNode () == Op0.getNode () && Op0 != Op1) {
5341+ SDValue CFRChain = Op0.getOperand (0 );
5342+ Register Reg = cast<RegisterSDNode>(Op0.getOperand (1 ))->getReg ();
5343+ if (CFRChain.getOpcode () == ISD::CopyToReg &&
5344+ cast<RegisterSDNode>(CFRChain.getOperand (1 ))->getReg () == Reg) {
5345+ SDValue Value = CFRChain.getOperand (2 );
5346+ return Value;
5347+ }
5348+ }
5349+
5350+ return SDValue ();
5351+ }
5352+
53255353SDValue NVPTXTargetLowering::PerformDAGCombine (SDNode *N,
53265354 DAGCombinerInfo &DCI) const {
53275355 CodeGenOptLevel OptLevel = getTargetMachine ().getOptLevel ();
@@ -5360,6 +5388,8 @@ SDValue NVPTXTargetLowering::PerformDAGCombine(SDNode *N,
53605388 return PerformORCombine (N, DCI, OptLevel);
53615389 case ISD::TRUNCATE:
53625390 return PerformTRUNCATECombine (N, DCI, OptLevel);
5391+ case ISD::BUILD_PAIR:
5392+ return PerformBUILD_PAIRCombine (N, DCI, OptLevel);
53635393 }
53645394 return SDValue ();
53655395}
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