Pre-commit tests

Author: pedroclobo

llvm/test/Transforms/InstSimplify/compare.ll

@@ -2724,6 +2724,45 @@ define i1 @icmp_nsw_false_5(i8 %V) {
   ret i1 %cmp
 }
 
+define i1 @icmp_nsw_false_6(i8 %V) {
+; CHECK-LABEL: @icmp_nsw_false_6(
+; CHECK-NEXT:    [[ADD:%.*]] = add i8 [[V:%.*]], 6
+; CHECK-NEXT:    [[ADDNSW:%.*]] = add nsw i8 [[V]], -1
+; CHECK-NEXT:    [[CMP:%.*]] = icmp sgt i8 [[ADD]], [[ADDNSW]]
+; CHECK-NEXT:    ret i1 [[CMP]]
+;
+  %add = add i8 %V, 6
+  %addnsw = add nsw i8 %V, -1
+  %cmp = icmp sgt i8 %add, %addnsw
+  ret i1 %cmp
+}
+
+define i1 @icmp_nsw_false_7(i8 %V) {
+; CHECK-LABEL: @icmp_nsw_false_7(
+; CHECK-NEXT:    [[ADD:%.*]] = add i8 [[V:%.*]], -1
+; CHECK-NEXT:    [[ADDNSW:%.*]] = add nsw i8 [[V]], 3
+; CHECK-NEXT:    [[CMP:%.*]] = icmp sle i8 [[ADD]], [[ADDNSW]]
+; CHECK-NEXT:    ret i1 [[CMP]]
+;
+  %add = add i8 %V, -1
+  %addnsw = add nsw i8 %V, 3
+  %cmp = icmp sle i8 %add, %addnsw
+  ret i1 %cmp
+}
+
+define i1 @icmp_nsw_false_8(i8 %V) {
+; CHECK-LABEL: @icmp_nsw_false_8(
+; CHECK-NEXT:    [[ADD:%.*]] = add i8 [[V:%.*]], -15
+; CHECK-NEXT:    [[ADDNSW:%.*]] = add nsw i8 [[V]], 42
+; CHECK-NEXT:    [[CMP:%.*]] = icmp sge i8 [[ADD]], [[ADDNSW]]
+; CHECK-NEXT:    ret i1 [[CMP]]
+;
+  %add = add i8 %V, -15
+  %addnsw = add nsw i8 %V, 42
+  %cmp = icmp sge i8 %add, %addnsw
+  ret i1 %cmp
+}
+
 define i1 @icmp_nsw_i8(i8 %V) {
 ; CHECK-LABEL: @icmp_nsw_i8(
 ; CHECK-NEXT:    ret i1 true
@@ -2868,6 +2907,42 @@ define i1 @icmp_nsw_11(i32 %V) {
   ret i1 %cmp
 }
 
+define i1 @icmp_nsw_12(i32 %V) {
+; CHECK-LABEL: @icmp_nsw_12(
+; CHECK-NEXT:    ret i1 true
+;
+  %add5 = add i32 %V, 2
+  %add6 = add nsw i32 %V, 3
+  %cmp = icmp slt i32 %add5, %add6
+  ret i1 %cmp
+}
+
+define i1 @icmp_nsw_13(i32 %V) {
+; CHECK-LABEL: @icmp_nsw_13(
+; CHECK-NEXT:    [[ADD5:%.*]] = add i32 [[V:%.*]], 7
+; CHECK-NEXT:    [[ADD6:%.*]] = add nsw i32 [[V]], 10
+; CHECK-NEXT:    [[CMP:%.*]] = icmp sle i32 [[ADD5]], [[ADD6]]
+; CHECK-NEXT:    ret i1 [[CMP]]
+;
+  %add5 = add i32 %V, 7
+  %add6 = add nsw i32 %V, 10
+  %cmp = icmp sle i32 %add5, %add6
+  ret i1 %cmp
+}
+
+define i1 @icmp_nsw_14(i32 %V) {
+; CHECK-LABEL: @icmp_nsw_14(
+; CHECK-NEXT:    [[ADD5:%.*]] = add i32 [[V:%.*]], 7
+; CHECK-NEXT:    [[ADD6:%.*]] = add nsw i32 [[V]], 10
+; CHECK-NEXT:    [[CMP:%.*]] = icmp sge i32 [[ADD5]], [[ADD6]]
+; CHECK-NEXT:    ret i1 [[CMP]]
+;
+  %add5 = add i32 %V, 7
+  %add6 = add nsw i32 %V, 10
+  %cmp = icmp sge i32 %add5, %add6
+  ret i1 %cmp
+}
+
 define i1 @icmp_nsw_nonpos(i32 %V) {
 ; CHECK-LABEL: @icmp_nsw_nonpos(
 ; CHECK-NEXT:    ret i1 false
@@ -2890,6 +2965,45 @@ define i1 @icmp_nsw_nonpos2(i32 %V) {
   ret i1 %cmp
 }
 
+define i1 @icmp_nsw_nonpos3(i32 %V) {
+; CHECK-LABEL: @icmp_nsw_nonpos3(
+; CHECK-NEXT:    [[ADD5:%.*]] = add i32 [[V:%.*]], -2
+; CHECK-NEXT:    [[ADD6:%.*]] = add nsw i32 [[V]], -5
+; CHECK-NEXT:    [[CMP:%.*]] = icmp sle i32 [[ADD5]], [[ADD6]]
+; CHECK-NEXT:    ret i1 [[CMP]]
+;
+  %add5 = add i32 %V, -2
+  %add6 = add nsw i32 %V, -5
+  %cmp = icmp sle i32 %add5, %add6
+  ret i1 %cmp
+}
+
+define i1 @icmp_nsw_nonpos4(i32 %V) {
+; CHECK-LABEL: @icmp_nsw_nonpos4(
+; CHECK-NEXT:    [[ADD5:%.*]] = add i32 [[V:%.*]], -10
+; CHECK-NEXT:    [[ADD6:%.*]] = add nsw i32 [[V]], -30
+; CHECK-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[ADD5]], [[ADD6]]
+; CHECK-NEXT:    ret i1 [[CMP]]
+;
+  %add5 = add i32 %V, -10
+  %add6 = add nsw i32 %V, -30
+  %cmp = icmp sgt i32 %add5, %add6
+  ret i1 %cmp
+}
+
+define i1 @icmp_nsw_nonpos5(i32 %V) {
+; CHECK-LABEL: @icmp_nsw_nonpos5(
+; CHECK-NEXT:    [[ADD5:%.*]] = add i32 [[V:%.*]], -15
+; CHECK-NEXT:    [[ADD6:%.*]] = add nsw i32 [[V]], -100
+; CHECK-NEXT:    [[CMP:%.*]] = icmp sge i32 [[ADD5]], [[ADD6]]
+; CHECK-NEXT:    ret i1 [[CMP]]
+;
+  %add5 = add i32 %V, -15
+  %add6 = add nsw i32 %V, -100
+  %cmp = icmp sge i32 %add5, %add6
+  ret i1 %cmp
+}
+
 declare i11 @llvm.ctpop.i11(i11)
 declare i73 @llvm.ctpop.i73(i73)
 declare <2 x i13> @llvm.ctpop.v2i13(<2 x i13>)