@@ -3480,57 +3480,56 @@ static bool isConstValidTrue(const TargetLowering &TLI, unsigned ScalarSizeBits,
34803480bool CombinerHelper::matchCombineBuildUnmerge (MachineInstr &MI,
34813481 MachineRegisterInfo &MRI,
34823482 Register &UnmergeSrc) const {
3483- assert (MI.getOpcode () == TargetOpcode::G_BUILD_VECTOR);
3484-
3485- unsigned BuildUseCount = MI.getNumOperands () - 1 ;
3483+ auto &BV = cast<GBuildVector>(MI);
34863484
3485+ unsigned BuildUseCount = BV.getNumSources ();
34873486 if (BuildUseCount % 2 != 0 )
34883487 return false ;
34893488
34903489 unsigned NumUnmerge = BuildUseCount / 2 ;
34913490
3492- // Check the first operand is an unmerge
3493- auto *MaybeUnmerge = getDefIgnoringCopies (MI.getOperand (1 ).getReg (), MRI);
3494- if (MaybeUnmerge->getOpcode () != TargetOpcode::G_UNMERGE_VALUES)
3491+ auto *Unmerge = getOpcodeDef<GUnmerge>(BV.getSourceReg (0 ), MRI);
3492+
3493+ // Check the first operand is an unmerge and has the correct number of
3494+ // operands
3495+ if (!Unmerge || Unmerge->getNumOperands () != NumUnmerge + 1 )
34953496 return false ;
34963497
3498+ UnmergeSrc = Unmerge->getSourceReg ();
3499+
34973500 LLT DstTy = MRI.getType (MI.getOperand (0 ).getReg ());
3498- LLT UnmergeSrcTy = MRI.getType (
3499- MaybeUnmerge->getOperand (MaybeUnmerge->getNumOperands () - 1 ).getReg ());
3501+ LLT UnmergeSrcTy = MRI.getType (UnmergeSrc);
35003502
35013503 // Ensure we only generate legal instructions post-legalizer
3502- if (!IsPreLegalize && ! isLegal ({TargetOpcode::G_CONCAT_VECTORS,
3503- {DstTy, UnmergeSrcTy , UnmergeSrcTy}}))
3504+ if (!IsPreLegalize &&
3505+ ! isLegal ({TargetOpcode::G_CONCAT_VECTORS, {DstTy , UnmergeSrcTy}}))
35043506 return false ;
35053507
35063508 // Check that all of the operands before the midpoint come from the same
35073509 // unmerge and are in the same order as they are used in the build_vector
35083510 for (unsigned I = 0 ; I < NumUnmerge; ++I) {
3509- auto MaybeUnmergeReg = MI. getOperand (I + 1 ). getReg ( );
3510- auto *Unmerge = getDefIgnoringCopies (MaybeUnmergeReg, MRI);
3511+ auto MaybeUnmergeReg = BV. getSourceReg (I );
3512+ auto *LoopUnmerge = getOpcodeDef<GUnmerge> (MaybeUnmergeReg, MRI);
35113513
3512- if (Unmerge != MaybeUnmerge )
3514+ if (!LoopUnmerge || LoopUnmerge != Unmerge )
35133515 return false ;
35143516
3515- if (Unmerge ->getOperand (I).getReg () != MaybeUnmergeReg)
3517+ if (LoopUnmerge ->getOperand (I).getReg () != MaybeUnmergeReg)
35163518 return false ;
35173519 }
35183520
35193521 // Check that all of the unmerged values are used
3520- if (MaybeUnmerge ->getNumDefs () != NumUnmerge)
3522+ if (Unmerge ->getNumDefs () != NumUnmerge)
35213523 return false ;
35223524
35233525 // Check that all of the operands after the mid point are undefs.
35243526 for (unsigned I = NumUnmerge; I < BuildUseCount; ++I) {
3525- auto *Undef = getDefIgnoringCopies (MI. getOperand (I + 1 ). getReg ( ), MRI);
3527+ auto *Undef = getDefIgnoringCopies (BV. getSourceReg (I ), MRI);
35263528
35273529 if (Undef->getOpcode () != TargetOpcode::G_IMPLICIT_DEF)
35283530 return false ;
35293531 }
35303532
3531- UnmergeSrc =
3532- MaybeUnmerge->getOperand (MaybeUnmerge->getNumOperands () - 1 ).getReg ();
3533-
35343533 return true ;
35353534}
35363535
@@ -8510,4 +8509,4 @@ bool CombinerHelper::matchSuboCarryOut(const MachineInstr &MI,
85108509 }
85118510
85128511 return false ;
8513- }
8512+ }
0 commit comments