[CodeGen] Add flags to RDDSP and WRDSP at emission time

This allows us to remove the hack that requires we remove the dead flag from the physical register.

Author: AZero13

llvm/lib/CodeGen/LiveVariables.cpp

@@ -534,10 +534,6 @@ void LiveVariables::runOnInstr(MachineInstr &MI,
         UseRegs.push_back(MOReg);
     } else {
       assert(MO.isDef());
-      // FIXME: We should not remove any dead flags. However the MIPS RDDSP
-      // instruction needs it at the moment: http://llvm.org/PR27116.
-      if (MOReg.isPhysical() && !MRI->isReserved(MOReg))
-        MO.setIsDead(false);
       DefRegs.push_back(MOReg);
     }
   }

llvm/lib/Target/Mips/MipsDSPInstrInfo.td

@@ -1470,3 +1470,11 @@ let AddedComplexity = 20 in {
 let AdditionalPredicates = [NotInMicroMips] in {
   def : DSPInstAlias<"wrdsp $rt", (WRDSP GPR32Opnd:$rt, 0x1F), 1>;
 }
+
+def RDDSP_Pseudo : Pseudo<(outs GPR32Opnd:$rd), (ins uimm10:$mask), []> {
+  let usesCustomInserter = 1;
+}
+
+def WRDSP_Pseudo : Pseudo<(outs), (ins GPR32Opnd:$rs, uimm10:$mask), []> {
+  let usesCustomInserter = 1;
+}

llvm/lib/Target/Mips/MipsISelLowering.cpp

@@ -1411,6 +1411,53 @@ static MachineBasicBlock *insertDivByZeroTrap(MachineInstr &MI,
   return &MBB;
 }
 
+MachineBasicBlock::iterator
+MipsTargetLowering::emitRDDSP(MachineInstr &MI, MachineBasicBlock *BB) const {
+  const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
+  unsigned DestReg = MI.getOperand(0).getReg();
+  unsigned Mask = MI.getOperand(1).getImm();
+  auto MIB = BuildMI(*BB, MI, MI.getDebugLoc(), TII.get(Mips::RDDSP), DestReg)
+                 .addImm(Mask);
+  if (Mask & 1)
+    MIB.addReg(Mips::DSPPos, RegState::Implicit);
+  if (Mask & 2)
+    MIB.addReg(Mips::DSPSCount, RegState::Implicit);
+  if (Mask & 4)
+    MIB.addReg(Mips::DSPCarry, RegState::Implicit);
+  if (Mask & 8)
+    MIB.addReg(Mips::DSPOutFlag, RegState::Implicit);
+  if (Mask & 16)
+    MIB.addReg(Mips::DSPCCond, RegState::Implicit);
+  if (Mask & 32)
+    MIB.addReg(Mips::DSPEFI, RegState::Implicit);
+  MI.eraseFromParent();
+  return MIB;
+}
+
+MachineBasicBlock::iterator
+MipsTargetLowering::emitWRDSP(MachineInstr &MI, MachineBasicBlock *BB) const {
+  const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
+  unsigned SrcReg = MI.getOperand(0).getReg();
+  unsigned Mask = MI.getOperand(1).getImm();
+  auto MIB = BuildMI(*BB, MI, MI.getDebugLoc(), TII.get(Mips::WRDSP))
+                 .addReg(SrcReg)
+                 .addImm(Mask);
+  if (Mask & 1)
+    MIB.addReg(Mips::DSPPos, RegState::ImplicitDefine);
+  if (Mask & 2)
+    MIB.addReg(Mips::DSPSCount, RegState::ImplicitDefine);
+  if (Mask & 4)
+    MIB.addReg(Mips::DSPCarry, RegState::ImplicitDefine);
+  if (Mask & 8)
+    MIB.addReg(Mips::DSPOutFlag, RegState::ImplicitDefine);
+  if (Mask & 16)
+    MIB.addReg(Mips::DSPCCond, RegState::ImplicitDefine);
+  if (Mask & 32)
+    MIB.addReg(Mips::DSPEFI, RegState::ImplicitDefine);
+  MI.eraseFromParent();
+  return MIB;
+}
+
 MachineBasicBlock *
 MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
                                                 MachineBasicBlock *BB) const {
@@ -1579,6 +1626,10 @@ MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
     return emitSTR_W(MI, BB);
   case Mips::STR_D:
     return emitSTR_D(MI, BB);
+  case Mips::RDDSP_Pseudo:
+    return emitRDDSP(MI, BB);
+  case Mips::WRDSP_Pseudo:
+    return emitWRDSP(MI, BB);
   }
 }
 

llvm/lib/Target/Mips/MipsISelLowering.h

@@ -744,6 +744,8 @@ class TargetRegisterClass;
     MachineBasicBlock *emitLDR_D(MachineInstr &MI, MachineBasicBlock *BB) const;
     MachineBasicBlock *emitSTR_W(MachineInstr &MI, MachineBasicBlock *BB) const;
     MachineBasicBlock *emitSTR_D(MachineInstr &MI, MachineBasicBlock *BB) const;
+    MachineBasicBlock *emitRDDSP(MachineInstr &MI, MachineBasicBlock *BB) const;
+    MachineBasicBlock *emitWRDSP(MachineInstr &MI, MachineBasicBlock *BB) const;
   };
 
   /// Create MipsTargetLowering objects.

llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp

@@ -44,32 +44,6 @@ void MipsSEDAGToDAGISelLegacy::getAnalysisUsage(AnalysisUsage &AU) const {
   SelectionDAGISelLegacy::getAnalysisUsage(AU);
 }
 
-void MipsSEDAGToDAGISel::addDSPCtrlRegOperands(bool IsDef, MachineInstr &MI,
-                                               MachineFunction &MF) {
-  MachineInstrBuilder MIB(MF, &MI);
-  unsigned Mask = MI.getOperand(1).getImm();
-  unsigned Flag =
-      IsDef ? RegState::ImplicitDefine : RegState::Implicit | RegState::Undef;
-
-  if (Mask & 1)
-    MIB.addReg(Mips::DSPPos, Flag);
-
-  if (Mask & 2)
-    MIB.addReg(Mips::DSPSCount, Flag);
-
-  if (Mask & 4)
-    MIB.addReg(Mips::DSPCarry, Flag);
-
-  if (Mask & 8)
-    MIB.addReg(Mips::DSPOutFlag, Flag);
-
-  if (Mask & 16)
-    MIB.addReg(Mips::DSPCCond, Flag);
-
-  if (Mask & 32)
-    MIB.addReg(Mips::DSPEFI, Flag);
-}
-
 MCRegister MipsSEDAGToDAGISel::getMSACtrlReg(const SDValue RegIdx) const {
   uint64_t RegNum = RegIdx->getAsZExtVal();
   return Mips::MSACtrlRegClass.getRegister(RegNum);
@@ -155,12 +129,6 @@ void MipsSEDAGToDAGISel::processFunctionAfterISel(MachineFunction &MF) {
   for (auto &MBB: MF) {
     for (auto &MI: MBB) {
       switch (MI.getOpcode()) {
-      case Mips::RDDSP:
-        addDSPCtrlRegOperands(false, MI, MF);
-        break;
-      case Mips::WRDSP:
-        addDSPCtrlRegOperands(true, MI, MF);
-        break;
       case Mips::BuildPairF64_64:
       case Mips::ExtractElementF64_64:
         if (!Subtarget->useOddSPReg()) {
@@ -231,8 +199,8 @@ void MipsSEDAGToDAGISel::selectAddE(SDNode *Node, const SDLoc &DL) const {
 
   SDValue OuFlag = CurDAG->getTargetConstant(20, DL, MVT::i32);
 
-  SDNode *DSPCtrlField = CurDAG->getMachineNode(Mips::RDDSP, DL, MVT::i32,
-                                                MVT::Glue, CstOne, InGlue);
+  SDNode *DSPCtrlField = CurDAG->getMachineNode(
+      Mips::RDDSP_Pseudo, DL, MVT::i32, MVT::Glue, CstOne, InGlue);
 
   SDNode *Carry = CurDAG->getMachineNode(
       Mips::EXT, DL, MVT::i32, SDValue(DSPCtrlField, 0), OuFlag, CstOne);
@@ -253,7 +221,7 @@ void MipsSEDAGToDAGISel::selectAddE(SDNode *Node, const SDLoc &DL) const {
   SDNode *DSPCtrlFinal =
       CurDAG->getMachineNode(Mips::INS, DL, MVT::i32, InsOps);
 
-  SDNode *WrDSP = CurDAG->getMachineNode(Mips::WRDSP, DL, MVT::Glue,
+  SDNode *WrDSP = CurDAG->getMachineNode(Mips::WRDSP_Pseudo, DL, MVT::Glue,
                                          SDValue(DSPCtrlFinal, 0), CstOne);
 
   SDValue Operands[3] = {LHS, RHS, SDValue(WrDSP, 0)};

llvm/lib/Target/Mips/MipsSEISelDAGToDAG.h

@@ -27,9 +27,6 @@ class MipsSEDAGToDAGISel : public MipsDAGToDAGISel {
 
   bool runOnMachineFunction(MachineFunction &MF) override;
 
-  void addDSPCtrlRegOperands(bool IsDef, MachineInstr &MI,
-                             MachineFunction &MF);
-
   MCRegister getMSACtrlReg(const SDValue RegIdx) const;
 
   bool replaceUsesWithZeroReg(MachineRegisterInfo *MRI, const MachineInstr&);