Skip to content

Commit ca10dac

Browse files
jthackrayjthackray
authored
[AArch64][llvm] Armv9.7-A: Add support for Virtual Memory Tagging (FEAT_MTETC) (#163158)
Add the following instructions for `FEAT_MTETC`, which is a part of `FEAT_VMTE` for Virtual Tagging: * `DC ZGBVA` * `DC GBVA` as documented here: * https://developer.arm.com/documentation/ddi0602/2025-09/ * https://developer.arm.com/documentation/109697/2025_09/2025-Architecture-Extensions
1 parent d30f18d commit ca10dac

File tree

9 files changed

+65
-1
lines changed

9 files changed

+65
-1
lines changed

‎clang/test/Driver/aarch64-v97a.c‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -33,3 +33,7 @@
3333
// RUN: %clang -target aarch64 -march=armv9.7a+mpamv2 -### -c %s 2>&1 | FileCheck -check-prefix=V97A-MPAMv2 %s
3434
// RUN: %clang -target aarch64 -march=armv9.7-a+mpamv2 -### -c %s 2>&1 | FileCheck -check-prefix=V97A-MPAMv2 %s
3535
// V97A-MPAMv2: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "generic" "-target-feature" "+v9.7a"{{.*}} "-target-feature" "+mpamv2"
36+
37+
// RUN: %clang -target aarch64 -march=armv9.7a+mtetc -### -c %s 2>&1 | FileCheck -check-prefix=V97A-MTETC %s
38+
// RUN: %clang -target aarch64 -march=armv9.7-a+mtetc -### -c %s 2>&1 | FileCheck -check-prefix=V97A-MTETC %s
39+
// V97A-MTETC: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "generic" "-target-feature" "+v9.7a"{{.*}} "-target-feature" "+mtetc"

‎clang/test/Driver/print-supported-extensions-aarch64.c‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -47,6 +47,7 @@
4747
// CHECK-NEXT: mops FEAT_MOPS Enable Armv8.8-A memcpy and memset acceleration instructions
4848
// CHECK-NEXT: mpamv2 FEAT_MPAMv2 Enable Armv9.7-A MPAMv2 Lookaside Buffer Invalidate instructions
4949
// CHECK-NEXT: memtag FEAT_MTE, FEAT_MTE2 Enable Memory Tagging Extension
50+
// CHECK-NEXT: mtetc FEAT_MTETC Enable Virtual Memory Tagging Extension
5051
// CHECK-NEXT: simd FEAT_AdvSIMD Enable Advanced SIMD instructions
5152
// CHECK-NEXT: occmo FEAT_OCCMO Enable Armv9.6-A Outer cacheable cache maintenance operations
5253
// CHECK-NEXT: pauth FEAT_PAuth Enable Armv8.3-A Pointer Authentication extension

‎llvm/lib/Target/AArch64/AArch64Features.td‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -601,6 +601,9 @@ def FeatureTLBID: ExtensionWithMArch<"tlbid", "TLBID", "FEAT_TLBID",
601601
def FeatureMPAMv2: ExtensionWithMArch<"mpamv2", "MPAMv2", "FEAT_MPAMv2",
602602
"Enable Armv9.7-A MPAMv2 Lookaside Buffer Invalidate instructions">;
603603

604+
def FeatureMTETC: ExtensionWithMArch<"mtetc", "MTETC", "FEAT_MTETC",
605+
"Enable Virtual Memory Tagging Extension">;
606+
604607
//===----------------------------------------------------------------------===//
605608
// Other Features
606609
//===----------------------------------------------------------------------===//

‎llvm/lib/Target/AArch64/AArch64InstrInfo.td‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -404,6 +404,8 @@ def HasTLBID : Predicate<"Subtarget->hasTLBID()">,
404404
AssemblerPredicateWithAll<(all_of FeatureTLBID), "tlbid">;
405405
def HasMPAMv2 : Predicate<"Subtarget->hasMPAMv2()">,
406406
AssemblerPredicateWithAll<(all_of FeatureMPAMv2), "mpamv2">;
407+
def HasMTETC : Predicate<"Subtarget->hasMTETC()">,
408+
AssemblerPredicateWithAll<(all_of FeatureMTETC), "mtetc">;
407409
def IsLE : Predicate<"Subtarget->isLittleEndian()">;
408410
def IsBE : Predicate<"!Subtarget->isLittleEndian()">;
409411
def IsWindows : Predicate<"Subtarget->isTargetWindows()">;

‎llvm/lib/Target/AArch64/AArch64SystemOperands.td‎

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -205,6 +205,7 @@ def lookupDCByName : SearchIndex {
205205
let Key = ["Name"];
206206
}
207207

208+
// Op1 CRn CRm Op2
208209
def : DC<"ZVA", 0b011, 0b0111, 0b0100, 0b001>;
209210
def : DC<"IVAC", 0b000, 0b0111, 0b0110, 0b001>;
210211
def : DC<"ISW", 0b000, 0b0111, 0b0110, 0b010>;
@@ -241,6 +242,11 @@ def : DC<"CIGDVAC", 0b011, 0b0111, 0b1110, 0b101>;
241242
def : DC<"GZVA", 0b011, 0b0111, 0b0100, 0b100>;
242243
}
243244

245+
let Requires = [{ {AArch64::FeatureMTETC} }] in {
246+
def : DC<"ZGBVA", 0b011, 0b0111, 0b0100, 0b101>;
247+
def : DC<"GBVA", 0b011, 0b0111, 0b0100, 0b111>;
248+
}
249+
244250
let Requires = [{ {AArch64::FeatureMEC} }] in {
245251
def : DC<"CIPAE", 0b100, 0b0111, 0b1110, 0b000>;
246252
def : DC<"CIGDPAE", 0b100, 0b0111, 0b1110, 0b111>;

‎llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3887,6 +3887,7 @@ static const struct Extension {
38873887
{"lscp", {AArch64::FeatureLSCP}},
38883888
{"tlbid", {AArch64::FeatureTLBID}},
38893889
{"mpamv2", {AArch64::FeatureMPAMv2}},
3890+
{"mtetc", {AArch64::FeatureMTETC}},
38903891
};
38913892

38923893
static void setRequiredFeatureString(FeatureBitset FBS, std::string &Str) {

‎llvm/test/MC/AArch64/armv9.7a-mtetc-diagnostics.s‎

Lines changed: 16 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,16 @@
1+
// RUN: not llvm-mc -triple=aarch64 -mattr=+mtetc -show-encoding < %s 2>&1 \
2+
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
3+
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
4+
// RUN: | FileCheck %s --check-prefix=CHECK-REQUIRES-MTETC
5+
6+
//------------------------------------------------------------------------------
7+
// FEAT_MTETC Extension instructions
8+
//------------------------------------------------------------------------------
9+
10+
dc zgbva
11+
// CHECK-ERROR: error: specified dc op requires a register
12+
// CHECK-REQUIRES-MTETC: DC ZGBVA requires: mtetc
13+
14+
dc gbva
15+
// CHECK-ERROR: error: specified dc op requires a register
16+
// CHECK-REQUIRES-MTETC: DC GBVA requires: mtetc

‎llvm/test/MC/AArch64/armv9.7a-mtetc.s‎

Lines changed: 29 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,29 @@
1+
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+mtetc < %s \
2+
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
3+
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
4+
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
5+
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+mtetc < %s \
6+
// RUN: | llvm-objdump -d --mattr=+mtetc --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-INST
7+
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+mtetc < %s \
8+
// RUN: | llvm-objdump -d --mattr=-mtetc --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-UNKNOWN
9+
// Disassemble encoding and check the re-encoding (-show-encoding) matches.
10+
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+mtetc < %s \
11+
// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
12+
// RUN: | llvm-mc -triple=aarch64 -mattr=+mtetc -disassemble -show-encoding \
13+
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
14+
15+
//------------------------------------------------------------------------------
16+
// FEAT_MTETC Extension instructions
17+
//------------------------------------------------------------------------------
18+
19+
dc zgbva, x0
20+
// CHECK-INST: dc zgbva, x0
21+
// CHECK-ENCODING: [0xa0,0x74,0x0b,0xd5]
22+
// CHECK-UNKNOWN: d50b74a0 sys #3, c7, c4, #5, x0
23+
// CHECK-ERROR: DC ZGBVA requires: mtetc
24+
25+
dc gbva, x0
26+
// CHECK-INST: dc gbva, x0
27+
// CHECK-ENCODING: [0xe0,0x74,0x0b,0xd5]
28+
// CHECK-UNKNOWN: d50b74e0 sys #3, c7, c4, #7, x0
29+
// CHECK-ERROR: DC GBVA requires: mtetc

‎llvm/unittests/TargetParser/TargetParserTest.cpp‎

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1445,7 +1445,7 @@ TEST(TargetParserTest, AArch64ExtensionFeatures) {
14451445
AArch64::AEK_SSVE_BITPERM, AArch64::AEK_SVESHA3,
14461446
AArch64::AEK_SVESM4, AArch64::AEK_CMH,
14471447
AArch64::AEK_LSCP, AArch64::AEK_TLBID,
1448-
AArch64::AEK_MPAMV2,
1448+
AArch64::AEK_MPAMV2, AArch64::AEK_MTETC,
14491449
};
14501450

14511451
std::vector<StringRef> Features;
@@ -1561,6 +1561,7 @@ TEST(TargetParserTest, AArch64ExtensionFeatures) {
15611561
EXPECT_TRUE(llvm::is_contained(Features, "+lscp"));
15621562
EXPECT_TRUE(llvm::is_contained(Features, "+tlbid"));
15631563
EXPECT_TRUE(llvm::is_contained(Features, "+mpamv2"));
1564+
EXPECT_TRUE(llvm::is_contained(Features, "+mtetc"));
15641565

15651566
// Assuming we listed every extension above, this should produce the same
15661567
// result.
@@ -1731,6 +1732,7 @@ TEST(TargetParserTest, AArch64ArchExtFeature) {
17311732
{"lscp", "nolscp", "+lscp", "-lscp"},
17321733
{"tlbid", "notlbid", "+tlbid", "-tlbid"},
17331734
{"mpamv2", "nompamv2", "+mpamv2", "-mpamv2"},
1735+
{"mtetc", "nomtetc", "+mtetc", "-mtetc"},
17341736
};
17351737

17361738
for (unsigned i = 0; i < std::size(ArchExt); i++) {

0 commit comments

Comments
 (0)