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[Targets] Migrate from atomic_load_8/16/32/64 to atomic_load_nonext_8/16/32/64. NFC (#137428)
This makes them more consistent with the checks performed by regular loads. We can't simply add IsNonExtLoad to the existing atomic_load_8/16/32/64 as that would affect out of tree targets.
1 parent 76d83e6 commit ca21508

25 files changed

+168
-158
lines changed

‎llvm/lib/Target/AArch64/AArch64InstrAtomics.td‎

Lines changed: 44 additions & 40 deletions
Original file line numberDiff line numberDiff line change
@@ -55,9 +55,9 @@ let Predicates = [HasRCPC] in {
5555
// 16-bit loads
5656
def : Pat<(acquiring_load<atomic_load_azext_16> GPR64sp:$ptr), (LDAPRH GPR64sp:$ptr)>;
5757
// 32-bit loads
58-
def : Pat<(acquiring_load<atomic_load_32> GPR64sp:$ptr), (LDAPRW GPR64sp:$ptr)>;
58+
def : Pat<(acquiring_load<atomic_load_nonext_32> GPR64sp:$ptr), (LDAPRW GPR64sp:$ptr)>;
5959
// 64-bit loads
60-
def : Pat<(acquiring_load<atomic_load_64> GPR64sp:$ptr), (LDAPRX GPR64sp:$ptr)>;
60+
def : Pat<(acquiring_load<atomic_load_nonext_64> GPR64sp:$ptr), (LDAPRX GPR64sp:$ptr)>;
6161
}
6262

6363
// 8-bit loads
@@ -93,62 +93,66 @@ def : Pat<(relaxed_load<atomic_load_azext_16>
9393
(LDURHHi GPR64sp:$Rn, simm9:$offset)>;
9494

9595
// 32-bit loads
96-
def : Pat<(seq_cst_load<atomic_load_32> GPR64sp:$ptr), (LDARW GPR64sp:$ptr)>;
97-
def : Pat<(acquiring_load<atomic_load_32> GPR64sp:$ptr), (LDARW GPR64sp:$ptr)>;
98-
def : Pat<(relaxed_load<atomic_load_32> (ro_Windexed32 GPR64sp:$Rn, GPR32:$Rm,
99-
ro_Wextend32:$extend)),
96+
def : Pat<(seq_cst_load<atomic_load_nonext_32> GPR64sp:$ptr),
97+
(LDARW GPR64sp:$ptr)>;
98+
def : Pat<(acquiring_load<atomic_load_nonext_32> GPR64sp:$ptr),
99+
(LDARW GPR64sp:$ptr)>;
100+
def : Pat<(relaxed_load<atomic_load_nonext_32>
101+
(ro_Windexed32 GPR64sp:$Rn, GPR32:$Rm, ro_Wextend32:$extend)),
100102
(LDRWroW GPR64sp:$Rn, GPR32:$Rm, ro_Wextend32:$extend)>;
101-
def : Pat<(relaxed_load<atomic_load_32> (ro_Xindexed32 GPR64sp:$Rn, GPR64:$Rm,
102-
ro_Xextend32:$extend)),
103+
def : Pat<(relaxed_load<atomic_load_nonext_32>
104+
(ro_Xindexed32 GPR64sp:$Rn, GPR64:$Rm, ro_Xextend32:$extend)),
103105
(LDRWroX GPR64sp:$Rn, GPR64:$Rm, ro_Xextend32:$extend)>;
104-
def : Pat<(relaxed_load<atomic_load_32> (am_indexed32 GPR64sp:$Rn,
105-
uimm12s4:$offset)),
106+
def : Pat<(relaxed_load<atomic_load_nonext_32>
107+
(am_indexed32 GPR64sp:$Rn, uimm12s4:$offset)),
106108
(LDRWui GPR64sp:$Rn, uimm12s4:$offset)>;
107-
def : Pat<(relaxed_load<atomic_load_32>
109+
def : Pat<(relaxed_load<atomic_load_nonext_32>
108110
(am_unscaled32 GPR64sp:$Rn, simm9:$offset)),
109111
(LDURWi GPR64sp:$Rn, simm9:$offset)>;
110112

111113
// 64-bit loads
112-
def : Pat<(seq_cst_load<atomic_load_64> GPR64sp:$ptr), (LDARX GPR64sp:$ptr)>;
113-
def : Pat<(acquiring_load<atomic_load_64> GPR64sp:$ptr), (LDARX GPR64sp:$ptr)>;
114-
def : Pat<(relaxed_load<atomic_load_64> (ro_Windexed64 GPR64sp:$Rn, GPR32:$Rm,
115-
ro_Wextend64:$extend)),
114+
def : Pat<(seq_cst_load<atomic_load_nonext_64> GPR64sp:$ptr),
115+
(LDARX GPR64sp:$ptr)>;
116+
def : Pat<(acquiring_load<atomic_load_nonext_64> GPR64sp:$ptr),
117+
(LDARX GPR64sp:$ptr)>;
118+
def : Pat<(relaxed_load<atomic_load_nonext_64>
119+
(ro_Windexed64 GPR64sp:$Rn, GPR32:$Rm, ro_Wextend64:$extend)),
116120
(LDRXroW GPR64sp:$Rn, GPR32:$Rm, ro_Wextend64:$extend)>;
117-
def : Pat<(relaxed_load<atomic_load_64> (ro_Xindexed64 GPR64sp:$Rn, GPR64:$Rm,
118-
ro_Xextend64:$extend)),
121+
def : Pat<(relaxed_load<atomic_load_nonext_64>
122+
(ro_Xindexed64 GPR64sp:$Rn, GPR64:$Rm, ro_Xextend64:$extend)),
119123
(LDRXroX GPR64sp:$Rn, GPR64:$Rm, ro_Xextend64:$extend)>;
120-
def : Pat<(relaxed_load<atomic_load_64> (am_indexed64 GPR64sp:$Rn,
121-
uimm12s8:$offset)),
124+
def : Pat<(relaxed_load<atomic_load_nonext_64>
125+
(am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
122126
(LDRXui GPR64sp:$Rn, uimm12s8:$offset)>;
123-
def : Pat<(relaxed_load<atomic_load_64>
127+
def : Pat<(relaxed_load<atomic_load_nonext_64>
124128
(am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
125129
(LDURXi GPR64sp:$Rn, simm9:$offset)>;
126130

127131
// FP 32-bit loads
128-
def : Pat<(f32 (bitconvert (i32 (relaxed_load<atomic_load_32> (ro_Windexed32 GPR64sp:$Rn, GPR32:$Rm,
129-
ro_Wextend32:$extend))))),
132+
def : Pat<(f32 (bitconvert (i32 (relaxed_load<atomic_load_nonext_32>
133+
(ro_Windexed32 GPR64sp:$Rn, GPR32:$Rm, ro_Wextend32:$extend))))),
130134
(LDRSroW GPR64sp:$Rn, GPR32:$Rm, ro_Wextend32:$extend)>;
131-
def : Pat<(f32 (bitconvert (i32 (relaxed_load<atomic_load_32> (ro_Xindexed32 GPR64sp:$Rn, GPR64:$Rm,
132-
ro_Xextend32:$extend))))),
135+
def : Pat<(f32 (bitconvert (i32 (relaxed_load<atomic_load_nonext_32>
136+
(ro_Xindexed32 GPR64sp:$Rn, GPR64:$Rm, ro_Xextend32:$extend))))),
133137
(LDRSroX GPR64sp:$Rn, GPR64:$Rm, ro_Xextend32:$extend)>;
134-
def : Pat<(f32 (bitconvert (i32 (relaxed_load<atomic_load_32> (am_indexed32 GPR64sp:$Rn,
135-
uimm12s8:$offset))))),
138+
def : Pat<(f32 (bitconvert (i32 (relaxed_load<atomic_load_nonext_32>
139+
(am_indexed32 GPR64sp:$Rn, uimm12s8:$offset))))),
136140
(LDRSui GPR64sp:$Rn, uimm12s8:$offset)>;
137-
def : Pat<(f32 (bitconvert (i32 (relaxed_load<atomic_load_32>
141+
def : Pat<(f32 (bitconvert (i32 (relaxed_load<atomic_load_nonext_32>
138142
(am_unscaled32 GPR64sp:$Rn, simm9:$offset))))),
139143
(LDURSi GPR64sp:$Rn, simm9:$offset)>;
140144

141145
// FP 64-bit loads
142-
def : Pat<(f64 (bitconvert (i64 (relaxed_load<atomic_load_64> (ro_Windexed64 GPR64sp:$Rn, GPR32:$Rm,
143-
ro_Wextend64:$extend))))),
146+
def : Pat<(f64 (bitconvert (i64 (relaxed_load<atomic_load_nonext_64>
147+
(ro_Windexed64 GPR64sp:$Rn, GPR32:$Rm, ro_Wextend64:$extend))))),
144148
(LDRDroW GPR64sp:$Rn, GPR32:$Rm, ro_Wextend64:$extend)>;
145-
def : Pat<(f64 (bitconvert (i64 (relaxed_load<atomic_load_64> (ro_Xindexed64 GPR64sp:$Rn, GPR64:$Rm,
146-
ro_Xextend64:$extend))))),
149+
def : Pat<(f64 (bitconvert (i64 (relaxed_load<atomic_load_nonext_64>
150+
(ro_Xindexed64 GPR64sp:$Rn, GPR64:$Rm, ro_Xextend64:$extend))))),
147151
(LDRDroX GPR64sp:$Rn, GPR64:$Rm, ro_Xextend64:$extend)>;
148-
def : Pat<(f64 (bitconvert (i64 (relaxed_load<atomic_load_64> (am_indexed64 GPR64sp:$Rn,
149-
uimm12s8:$offset))))),
152+
def : Pat<(f64 (bitconvert (i64 (relaxed_load<atomic_load_nonext_64>
153+
(am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))))),
150154
(LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
151-
def : Pat<(f64 (bitconvert (i64 (relaxed_load<atomic_load_64>
155+
def : Pat<(f64 (bitconvert (i64 (relaxed_load<atomic_load_nonext_64>
152156
(am_unscaled64 GPR64sp:$Rn, simm9:$offset))))),
153157
(LDURDi GPR64sp:$Rn, simm9:$offset)>;
154158

@@ -561,16 +565,16 @@ let Predicates = [HasLSFE] in {
561565
let Predicates = [HasRCPC3, HasNEON] in {
562566
// LDAP1 loads
563567
def : Pat<(vector_insert (v2i64 VecListOne128:$Rd),
564-
(i64 (acquiring_load<atomic_load_64> GPR64sp:$Rn)), (i64 VectorIndexD:$idx)),
568+
(i64 (acquiring_load<atomic_load_nonext_64> GPR64sp:$Rn)), (i64 VectorIndexD:$idx)),
565569
(LDAP1 VecListOne128:$Rd, VectorIndexD:$idx, GPR64sp:$Rn)>;
566570
def : Pat<(vector_insert (v2f64 VecListOne128:$Rd),
567-
(f64 (bitconvert (i64 (acquiring_load<atomic_load_64> GPR64sp:$Rn)))), (i64 VectorIndexD:$idx)),
571+
(f64 (bitconvert (i64 (acquiring_load<atomic_load_nonext_64> GPR64sp:$Rn)))), (i64 VectorIndexD:$idx)),
568572
(LDAP1 VecListOne128:$Rd, VectorIndexD:$idx, GPR64sp:$Rn)>;
569573
def : Pat<(v1i64 (scalar_to_vector
570-
(i64 (acquiring_load<atomic_load_64> GPR64sp:$Rn)))),
574+
(i64 (acquiring_load<atomic_load_nonext_64> GPR64sp:$Rn)))),
571575
(EXTRACT_SUBREG (LDAP1 (v2i64 (IMPLICIT_DEF)), (i64 0), GPR64sp:$Rn), dsub)>;
572576
def : Pat<(v1f64 (scalar_to_vector
573-
(f64 (bitconvert (i64 (acquiring_load<atomic_load_64> GPR64sp:$Rn)))))),
577+
(f64 (bitconvert (i64 (acquiring_load<atomic_load_nonext_64> GPR64sp:$Rn)))))),
574578
(EXTRACT_SUBREG (LDAP1 (v2f64 (IMPLICIT_DEF)), (i64 0), GPR64sp:$Rn), dsub)>;
575579

576580
// STL1 stores
@@ -597,10 +601,10 @@ let Predicates = [HasRCPC_IMMO, UseLDAPUR] in {
597601
def : Pat<(acquiring_load<atomic_load_azext_16>
598602
(am_unscaled16 GPR64sp:$Rn, simm9:$offset)),
599603
(LDAPURHi GPR64sp:$Rn, simm9:$offset)>;
600-
def : Pat<(acquiring_load<atomic_load_32>
604+
def : Pat<(acquiring_load<atomic_load_nonext_32>
601605
(am_unscaled32 GPR64sp:$Rn, simm9:$offset)),
602606
(LDAPURi GPR64sp:$Rn, simm9:$offset)>;
603-
def : Pat<(acquiring_load<atomic_load_64>
607+
def : Pat<(acquiring_load<atomic_load_nonext_64>
604608
(am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
605609
(LDAPURXi GPR64sp:$Rn, simm9:$offset)>;
606610
}

‎llvm/lib/Target/AMDGPU/AMDGPUInstructions.td‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -502,15 +502,15 @@ def zextloadi16_#as : PatFrag<(ops node:$ptr), (zextloadi16 node:$ptr)> {
502502
let IsLoad = 1;
503503
}
504504

505-
def atomic_load_16_#as : PatFrag<(ops node:$ptr), (atomic_load_16 node:$ptr)> {
505+
def atomic_load_nonext_16_#as : PatFrag<(ops node:$ptr), (atomic_load_nonext_16 node:$ptr)> {
506506
let IsAtomic = 1;
507507
}
508508

509-
def atomic_load_32_#as : PatFrag<(ops node:$ptr), (atomic_load_32 node:$ptr)> {
509+
def atomic_load_nonext_32_#as : PatFrag<(ops node:$ptr), (atomic_load_nonext_32 node:$ptr)> {
510510
let IsAtomic = 1;
511511
}
512512

513-
def atomic_load_64_#as : PatFrag<(ops node:$ptr), (atomic_load_64 node:$ptr)> {
513+
def atomic_load_nonext_64_#as : PatFrag<(ops node:$ptr), (atomic_load_nonext_64 node:$ptr)> {
514514
let IsAtomic = 1;
515515
}
516516

‎llvm/lib/Target/AMDGPU/BUFInstructions.td‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -959,7 +959,7 @@ defm : MUBUF_Pseudo_Load_Pats<"BUFFER_LOAD_USHORT", i32, atomic_load_aext_16_glo
959959
defm : MUBUF_Pseudo_Load_Pats<"BUFFER_LOAD_USHORT", i32, atomic_load_zext_16_global>;
960960
defm : MUBUF_Pseudo_Load_Pats<"BUFFER_LOAD_UBYTE", i16, atomic_load_aext_8_global>;
961961
defm : MUBUF_Pseudo_Load_Pats<"BUFFER_LOAD_UBYTE", i16, atomic_load_zext_8_global>;
962-
defm : MUBUF_Pseudo_Load_Pats<"BUFFER_LOAD_USHORT", i16, atomic_load_16_global>;
962+
defm : MUBUF_Pseudo_Load_Pats<"BUFFER_LOAD_USHORT", i16, atomic_load_nonext_16_global>;
963963
defm : MUBUF_Pseudo_Load_Pats<"BUFFER_LOAD_UBYTE", i32, extloadi8_global>;
964964
defm : MUBUF_Pseudo_Load_Pats<"BUFFER_LOAD_UBYTE", i32, zextloadi8_global>;
965965
defm : MUBUF_Pseudo_Load_Pats<"BUFFER_LOAD_SBYTE", i32, sextloadi8_global>;
@@ -1933,8 +1933,8 @@ def : MUBUFLoad_PatternADDR64 <BUFFER_LOAD_SSHORT_ADDR64, i32, sextloadi16_const
19331933
def : MUBUFLoad_PatternADDR64 <BUFFER_LOAD_USHORT_ADDR64, i32, extloadi16_constant>;
19341934
def : MUBUFLoad_PatternADDR64 <BUFFER_LOAD_USHORT_ADDR64, i32, zextloadi16_constant>;
19351935

1936-
defm : MUBUFLoad_Atomic_Pattern <BUFFER_LOAD_DWORD_ADDR64, BUFFER_LOAD_DWORD_OFFSET, i32, atomic_load_32_global>;
1937-
defm : MUBUFLoad_Atomic_Pattern <BUFFER_LOAD_DWORDX2_ADDR64, BUFFER_LOAD_DWORDX2_OFFSET, i64, atomic_load_64_global>;
1936+
defm : MUBUFLoad_Atomic_Pattern <BUFFER_LOAD_DWORD_ADDR64, BUFFER_LOAD_DWORD_OFFSET, i32, atomic_load_nonext_32_global>;
1937+
defm : MUBUFLoad_Atomic_Pattern <BUFFER_LOAD_DWORDX2_ADDR64, BUFFER_LOAD_DWORDX2_OFFSET, i64, atomic_load_nonext_64_global>;
19381938
} // End SubtargetPredicate = isGFX6GFX7
19391939

19401940
multiclass MUBUFLoad_PatternOffset_Common <string Instr, ValueType vt,

‎llvm/lib/Target/AMDGPU/DSInstructions.td‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -859,12 +859,12 @@ defm : DSReadPat_t16 <DS_READ_U8, i16, "atomic_load_zext_8_local">;
859859
defm : DSReadPat_mc <DS_READ_U8, i32, "atomic_load_zext_8_local">;
860860
defm : DSReadPat_t16 <DS_READ_I8, i16, "atomic_load_sext_8_local">;
861861
defm : DSReadPat_mc <DS_READ_I8, i32, "atomic_load_sext_8_local">;
862-
defm : DSReadPat_t16 <DS_READ_U16, i16, "atomic_load_16_local">;
862+
defm : DSReadPat_t16 <DS_READ_U16, i16, "atomic_load_nonext_16_local">;
863863
defm : DSReadPat_mc <DS_READ_U16, i32, "atomic_load_aext_16_local">;
864864
defm : DSReadPat_mc <DS_READ_U16, i32, "atomic_load_zext_16_local">;
865865
defm : DSReadPat_mc <DS_READ_I16, i32, "atomic_load_sext_16_local">;
866-
defm : DSReadPat_mc <DS_READ_B32, i32, "atomic_load_32_local">;
867-
defm : DSReadPat_mc <DS_READ_B64, i64, "atomic_load_64_local">;
866+
defm : DSReadPat_mc <DS_READ_B32, i32, "atomic_load_nonext_32_local">;
867+
defm : DSReadPat_mc <DS_READ_B64, i64, "atomic_load_nonext_64_local">;
868868

869869
let OtherPredicates = [D16PreservesUnusedBits] in {
870870
// TODO: Atomic loads

‎llvm/lib/Target/AMDGPU/FLATInstructions.td‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1541,7 +1541,7 @@ def : FlatLoadPat <FLAT_LOAD_UBYTE, atomic_load_aext_8_flat, i16>;
15411541
def : FlatLoadPat <FLAT_LOAD_UBYTE, atomic_load_zext_8_flat, i32>;
15421542
def : FlatLoadPat <FLAT_LOAD_UBYTE, atomic_load_zext_8_flat, i16>;
15431543
def : FlatLoadPat <FLAT_LOAD_USHORT, atomic_load_aext_16_flat, i32>;
1544-
def : FlatLoadPat <FLAT_LOAD_USHORT, atomic_load_16_flat, i16>;
1544+
def : FlatLoadPat <FLAT_LOAD_USHORT, atomic_load_nonext_16_flat, i16>;
15451545
def : FlatLoadPat <FLAT_LOAD_USHORT, atomic_load_zext_16_flat, i32>;
15461546
def : FlatLoadPat <FLAT_LOAD_UBYTE, extloadi8_flat, i32>;
15471547
def : FlatLoadPat <FLAT_LOAD_UBYTE, zextloadi8_flat, i32>;
@@ -1573,8 +1573,8 @@ let OtherPredicates = [D16PreservesUnusedBits, HasFlatAddressSpace], True16Predi
15731573
def : FlatStorePat <FLAT_STORE_SHORT_t16, store_flat, i16>;
15741574
} // End let OtherPredicates = [D16PreservesUnusedBits, HasFlatAddressSpace], True16Predicate = UseRealTrue16Insts
15751575

1576-
def : FlatLoadPat <FLAT_LOAD_DWORD, atomic_load_32_flat, i32>;
1577-
def : FlatLoadPat <FLAT_LOAD_DWORDX2, atomic_load_64_flat, i64>;
1576+
def : FlatLoadPat <FLAT_LOAD_DWORD, atomic_load_nonext_32_flat, i32>;
1577+
def : FlatLoadPat <FLAT_LOAD_DWORDX2, atomic_load_nonext_64_flat, i64>;
15781578

15791579
def : FlatStorePat <FLAT_STORE_BYTE, truncstorei8_flat, i32>;
15801580
def : FlatStorePat <FLAT_STORE_SHORT, truncstorei16_flat, i32>;
@@ -1682,7 +1682,7 @@ defm : GlobalFLATLoadPats <GLOBAL_LOAD_UBYTE, atomic_load_aext_8_global, i16>;
16821682
defm : GlobalFLATLoadPats <GLOBAL_LOAD_UBYTE, atomic_load_zext_8_global, i32>;
16831683
defm : GlobalFLATLoadPats <GLOBAL_LOAD_UBYTE, atomic_load_zext_8_global, i16>;
16841684
defm : GlobalFLATLoadPats <GLOBAL_LOAD_USHORT, atomic_load_aext_16_global, i32>;
1685-
defm : GlobalFLATLoadPats <GLOBAL_LOAD_USHORT, atomic_load_16_global, i16>;
1685+
defm : GlobalFLATLoadPats <GLOBAL_LOAD_USHORT, atomic_load_nonext_16_global, i16>;
16861686
defm : GlobalFLATLoadPats <GLOBAL_LOAD_USHORT, atomic_load_zext_16_global, i32>;
16871687
defm : GlobalFLATLoadPats <GLOBAL_LOAD_USHORT, atomic_load_zext_16_global, i16>;
16881688
defm : GlobalFLATLoadPats <GLOBAL_LOAD_SBYTE, atomic_load_sext_8_global, i32>;
@@ -1733,8 +1733,8 @@ defm : GlobalFLATStorePats <GLOBAL_STORE_DWORDX4, store_global, vt>;
17331733
// There is no distinction for atomic load lowering during selection;
17341734
// the memory legalizer will set the cache bits and insert the
17351735
// appropriate waits.
1736-
defm : GlobalFLATLoadPats <GLOBAL_LOAD_DWORD, atomic_load_32_global, i32>;
1737-
defm : GlobalFLATLoadPats <GLOBAL_LOAD_DWORDX2, atomic_load_64_global, i64>;
1736+
defm : GlobalFLATLoadPats <GLOBAL_LOAD_DWORD, atomic_load_nonext_32_global, i32>;
1737+
defm : GlobalFLATLoadPats <GLOBAL_LOAD_DWORDX2, atomic_load_nonext_64_global, i64>;
17381738

17391739
defm : GlobalFLATStorePats <GLOBAL_STORE_BYTE, truncstorei8_global, i32>;
17401740
defm : GlobalFLATStorePats <GLOBAL_STORE_SHORT, truncstorei16_global, i32>;

‎llvm/lib/Target/AMDGPU/SIInstrInfo.td‎

Lines changed: 18 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -361,6 +361,12 @@ def load_glue : PatFrag <(ops node:$ptr), (unindexedload_glue node:$ptr)> {
361361
let IsNonExtLoad = 1;
362362
}
363363

364+
def atomic_load_nonext_glue :
365+
PatFrag<(ops node:$ptr), (AMDGPUatomic_ld_glue node:$ptr)> {
366+
let IsAtomic = true; // FIXME: Should be IsLoad and/or IsAtomic?
367+
let IsNonExtLoad = true;
368+
}
369+
364370
def atomic_load_zext_glue :
365371
PatFrag<(ops node:$ptr), (AMDGPUatomic_ld_glue node:$ptr)> {
366372
let IsAtomic = true; // FIXME: Should be IsLoad and/or IsAtomic?
@@ -379,20 +385,20 @@ def atomic_load_aext_glue :
379385
let IsAnyExtLoad = true;
380386
}
381387

382-
def atomic_load_16_glue : PatFrag<(ops node:$ptr),
383-
(AMDGPUatomic_ld_glue node:$ptr)> {
388+
def atomic_load_nonext_16_glue : PatFrag<(ops node:$ptr),
389+
(atomic_load_nonext_glue node:$ptr)> {
384390
let IsAtomic = 1;
385391
let MemoryVT = i16;
386392
}
387393

388-
def atomic_load_32_glue : PatFrag<(ops node:$ptr),
389-
(AMDGPUatomic_ld_glue node:$ptr)> {
394+
def atomic_load_nonext_32_glue : PatFrag<(ops node:$ptr),
395+
(atomic_load_nonext_glue node:$ptr)> {
390396
let IsAtomic = 1;
391397
let MemoryVT = i32;
392398
}
393399

394-
def atomic_load_64_glue : PatFrag<(ops node:$ptr),
395-
(AMDGPUatomic_ld_glue node:$ptr)> {
400+
def atomic_load_nonext_64_glue : PatFrag<(ops node:$ptr),
401+
(atomic_load_nonext_glue node:$ptr)> {
396402
let IsAtomic = 1;
397403
let MemoryVT = i64;
398404
}
@@ -506,12 +512,12 @@ def load_align16_local_m0 : PatFrag<(ops node:$ptr),
506512
}
507513

508514
let IsAtomic = 1, AddressSpaces = LoadAddress_local.AddrSpaces in {
509-
def atomic_load_16_local_m0 : PatFrag<(ops node:$ptr),
510-
(atomic_load_16_glue node:$ptr)>;
511-
def atomic_load_32_local_m0 : PatFrag<(ops node:$ptr),
512-
(atomic_load_32_glue node:$ptr)>;
513-
def atomic_load_64_local_m0 : PatFrag<(ops node:$ptr),
514-
(atomic_load_64_glue node:$ptr)>;
515+
def atomic_load_nonext_16_local_m0 : PatFrag<(ops node:$ptr),
516+
(atomic_load_nonext_16_glue node:$ptr)>;
517+
def atomic_load_nonext_32_local_m0 : PatFrag<(ops node:$ptr),
518+
(atomic_load_nonext_32_glue node:$ptr)>;
519+
def atomic_load_nonext_64_local_m0 : PatFrag<(ops node:$ptr),
520+
(atomic_load_nonext_64_glue node:$ptr)>;
515521

516522
def atomic_load_zext_8_local_m0 : PatFrag<(ops node:$ptr),
517523
(atomic_load_zext_8_glue node:$ptr)>;

‎llvm/lib/Target/ARM/ARMInstrInfo.td‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -5384,7 +5384,7 @@ class acquiring_load<PatFrags base>
53845384

53855385
def atomic_load_azext_acquire_8 : acquiring_load<atomic_load_azext_8>;
53865386
def atomic_load_azext_acquire_16 : acquiring_load<atomic_load_azext_16>;
5387-
def atomic_load_acquire_32 : acquiring_load<atomic_load_32>;
5387+
def atomic_load_nonext_acquire_32 : acquiring_load<atomic_load_nonext_32>;
53885388

53895389
class releasing_store<PatFrag base>
53905390
: PatFrag<(ops node:$ptr, node:$val), (base node:$val, node:$ptr), [{
@@ -5399,7 +5399,7 @@ def atomic_store_release_32 : releasing_store<atomic_store_32>;
53995399
let AddedComplexity = 8 in {
54005400
def : ARMPat<(atomic_load_azext_acquire_8 addr_offset_none:$addr), (LDAB addr_offset_none:$addr)>;
54015401
def : ARMPat<(atomic_load_azext_acquire_16 addr_offset_none:$addr), (LDAH addr_offset_none:$addr)>;
5402-
def : ARMPat<(atomic_load_acquire_32 addr_offset_none:$addr), (LDA addr_offset_none:$addr)>;
5402+
def : ARMPat<(atomic_load_nonext_acquire_32 addr_offset_none:$addr), (LDA addr_offset_none:$addr)>;
54035403
def : ARMPat<(atomic_store_release_8 addr_offset_none:$addr, GPR:$val), (STLB GPR:$val, addr_offset_none:$addr)>;
54045404
def : ARMPat<(atomic_store_release_16 addr_offset_none:$addr, GPR:$val), (STLH GPR:$val, addr_offset_none:$addr)>;
54055405
def : ARMPat<(atomic_store_release_32 addr_offset_none:$addr, GPR:$val), (STL GPR:$val, addr_offset_none:$addr)>;
@@ -6220,9 +6220,9 @@ def : ARMPat<(atomic_load_azext_8 addrmode_imm12:$src),
62206220
(LDRBi12 addrmode_imm12:$src)>;
62216221
def : ARMPat<(atomic_load_azext_16 addrmode3:$src),
62226222
(LDRH addrmode3:$src)>;
6223-
def : ARMPat<(atomic_load_32 ldst_so_reg:$src),
6223+
def : ARMPat<(atomic_load_nonext_32 ldst_so_reg:$src),
62246224
(LDRrs ldst_so_reg:$src)>;
6225-
def : ARMPat<(atomic_load_32 addrmode_imm12:$src),
6225+
def : ARMPat<(atomic_load_nonext_32 addrmode_imm12:$src),
62266226
(LDRi12 addrmode_imm12:$src)>;
62276227
def : ARMPat<(atomic_store_8 GPR:$val, ldst_so_reg:$ptr),
62286228
(STRBrs GPR:$val, ldst_so_reg:$ptr)>;

‎llvm/lib/Target/ARM/ARMInstrThumb.td‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1705,9 +1705,9 @@ def : T1Pat<(atomic_load_azext_16 t_addrmode_is2:$src),
17051705
(tLDRHi t_addrmode_is2:$src)>;
17061706
def : T1Pat<(atomic_load_azext_16 t_addrmode_rr:$src),
17071707
(tLDRHr t_addrmode_rr:$src)>;
1708-
def : T1Pat<(atomic_load_32 t_addrmode_is4:$src),
1708+
def : T1Pat<(atomic_load_nonext_32 t_addrmode_is4:$src),
17091709
(tLDRi t_addrmode_is4:$src)>;
1710-
def : T1Pat<(atomic_load_32 t_addrmode_rr:$src),
1710+
def : T1Pat<(atomic_load_nonext_32 t_addrmode_rr:$src),
17111711
(tLDRr t_addrmode_rr:$src)>;
17121712
def : T1Pat<(atomic_store_8 tGPR:$val, t_addrmode_is1:$ptr),
17131713
(tSTRBi tGPR:$val, t_addrmode_is1:$ptr)>;

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