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[GISel] Remove unnecessary MachineVerifier checks for G_ABDS/G_ABDU. (#120014)
These are declared to use a single type index for all operands in GenericOpcodes.td and the verifier knows how to check that all operands with the same type index match.
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2 files changed

+10
-28
lines changed

2 files changed

+10
-28
lines changed

llvm/lib/CodeGen/MachineVerifier.cpp

Lines changed: 0 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -1586,31 +1586,6 @@ void MachineVerifier::verifyPreISelGenericInstruction(const MachineInstr *MI) {
15861586

15871587
break;
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}
1589-
case TargetOpcode::G_ABDS:
1590-
case TargetOpcode::G_ABDU: {
1591-
LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1592-
LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
1593-
LLT SrcTy2 = MRI->getType(MI->getOperand(2).getReg());
1594-
1595-
if ((DstTy.isVector() != SrcTy.isVector()) ||
1596-
(DstTy.isVector() &&
1597-
DstTy.getElementCount() != SrcTy.getElementCount())) {
1598-
report("Generic vector abds/abdu must preserve number of lanes", MI);
1599-
break;
1600-
}
1601-
1602-
if (SrcTy != SrcTy2) {
1603-
report("Generic abds/abdu must have same input types", MI);
1604-
break;
1605-
}
1606-
1607-
if (DstTy != SrcTy) {
1608-
report("Generic abds/abdu must have same input and output types", MI);
1609-
break;
1610-
}
1611-
1612-
break;
1613-
}
16141589
case TargetOpcode::G_SCMP:
16151590
case TargetOpcode::G_UCMP: {
16161591
LLT DstTy = MRI->getType(MI->getOperand(0).getReg());

llvm/test/MachineVerifier/test_abd_su.mir

Lines changed: 10 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -8,25 +8,32 @@ body: |
88
99
%2:_(p0) = G_IMPLICIT_DEF
1010
%3:_(p0) = G_IMPLICIT_DEF
11+
; CHECK: Type mismatch in generic instruction
12+
; CHECK: Type mismatch in generic instruction
1113
%4:_(s1) = G_ABDS %2, %3
1214
1315
%12:_(s64) = G_IMPLICIT_DEF
1416
%13:_(s64) = G_IMPLICIT_DEF
17+
; CHECK: Type mismatch in generic instruction
18+
; CHECK: Type mismatch in generic instruction
1519
%14:_(p0) = G_ABDS %12, %13
1620
1721
%23:_(<2 x s32>) = G_IMPLICIT_DEF
1822
%24:_(<2 x s32>) = G_IMPLICIT_DEF
19-
; CHECK: Generic vector abds/abdu must preserve number of lanes
23+
; CHECK: Type mismatch in generic instruction
24+
; CHECK: Type mismatch in generic instruction
2025
%5:_(s1) = G_ABDU %23, %24
2126
2227
%15:_(s32) = G_CONSTANT i32 0
2328
%16:_(s64) = G_CONSTANT i64 2
24-
; CHECK: Generic abds/abdu must have same input types
29+
; CHECK: Type mismatch in generic instruction
30+
; CHECK: Type mismatch in generic instruction
2531
%17:_(s1) = G_ABDU %15, %16
2632
2733
%18:_(s64) = G_CONSTANT i64 0
2834
%19:_(s64) = G_CONSTANT i64 2
29-
; CHECK: Generic abds/abdu must have same input and output types
35+
; CHECK: Type mismatch in generic instruction
36+
; CHECK: Type mismatch in generic instruction
3037
%20:_(s1) = G_ABDU %18, %19
3138
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...

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