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[SelectionDAG] Rename CallOptions::IsSExt to IsSigned. NFC (#118574)
This is eventually passed to shouldSignExtendTypeInLibCall which calls it IsSigned.
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5 files changed

+18
-18
lines changed

5 files changed

+18
-18
lines changed

‎llvm/include/llvm/CodeGen/TargetLowering.h‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -4713,18 +4713,18 @@ class TargetLowering : public TargetLoweringBase {
47134713
// shouldExtendTypeInLibCall can get the original type before soften.
47144714
ArrayRef<EVT> OpsVTBeforeSoften;
47154715
EVT RetVTBeforeSoften;
4716-
bool IsSExt : 1;
4716+
bool IsSigned : 1;
47174717
bool DoesNotReturn : 1;
47184718
bool IsReturnValueUsed : 1;
47194719
bool IsPostTypeLegalization : 1;
47204720
bool IsSoften : 1;
47214721

47224722
MakeLibCallOptions()
4723-
: IsSExt(false), DoesNotReturn(false), IsReturnValueUsed(true),
4723+
: IsSigned(false), DoesNotReturn(false), IsReturnValueUsed(true),
47244724
IsPostTypeLegalization(false), IsSoften(false) {}
47254725

4726-
MakeLibCallOptions &setSExt(bool Value = true) {
4727-
IsSExt = Value;
4726+
MakeLibCallOptions &setIsSigned(bool Value = true) {
4727+
IsSigned = Value;
47284728
return *this;
47294729
}
47304730

‎llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4794,7 +4794,7 @@ void SelectionDAGLegalize::ConvertNodeToLibcall(SDNode *Node) {
47944794
SDValue Op = DAG.getNode(Signed ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, dl,
47954795
NVT, Node->getOperand(IsStrict ? 1 : 0));
47964796
TargetLowering::MakeLibCallOptions CallOptions;
4797-
CallOptions.setSExt(Signed);
4797+
CallOptions.setIsSigned(Signed);
47984798
std::pair<SDValue, SDValue> Tmp =
47994799
TLI.makeLibCall(DAG, LC, RVT, Op, CallOptions, dl, Chain);
48004800
Results.push_back(Tmp.first);

‎llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1044,7 +1044,7 @@ SDValue DAGTypeLegalizer::SoftenFloatRes_XINT_TO_FP(SDNode *N) {
10441044
SDValue Op = DAG.getNode(Signed ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, dl,
10451045
NVT, N->getOperand(IsStrict ? 1 : 0));
10461046
TargetLowering::MakeLibCallOptions CallOptions;
1047-
CallOptions.setSExt(Signed);
1047+
CallOptions.setIsSigned(Signed);
10481048
CallOptions.setTypeListBeforeSoften(SVT, RVT, true);
10491049
std::pair<SDValue, SDValue> Tmp =
10501050
TLI.makeLibCall(DAG, LC, TLI.getTypeToTransformTo(*DAG.getContext(), RVT),
@@ -2099,7 +2099,7 @@ void DAGTypeLegalizer::ExpandFloatRes_XINT_TO_FP(SDNode *N, SDValue &Lo,
20992099
assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported XINT_TO_FP!");
21002100

21012101
TargetLowering::MakeLibCallOptions CallOptions;
2102-
CallOptions.setSExt(true);
2102+
CallOptions.setIsSigned(true);
21032103
std::pair<SDValue, SDValue> Tmp =
21042104
TLI.makeLibCall(DAG, LC, VT, Src, CallOptions, dl, Chain);
21052105
if (Strict)

‎llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp‎

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -2601,7 +2601,7 @@ SDValue DAGTypeLegalizer::PromoteIntOp_ExpOp(SDNode *N) {
26012601
N->getOperand(1 + OpOffset).getValueType().getSizeInBits() &&
26022602
"POWI exponent should match with sizeof(int) when doing the libcall.");
26032603
TargetLowering::MakeLibCallOptions CallOptions;
2604-
CallOptions.setSExt(true);
2604+
CallOptions.setIsSigned(true);
26052605
SDValue Ops[2] = {N->getOperand(0 + OpOffset), N->getOperand(1 + OpOffset)};
26062606
std::pair<SDValue, SDValue> Tmp = TLI.makeLibCall(
26072607
DAG, LC, N->getValueType(0), Ops, CallOptions, SDLoc(N), Chain);
@@ -4006,7 +4006,7 @@ void DAGTypeLegalizer::ExpandIntRes_FP_TO_XINT(SDNode *N, SDValue &Lo,
40064006
if (getTypeAction(Op.getValueType()) == TargetLowering::TypeSoftenFloat)
40074007
CallOptions.setTypeListBeforeSoften(OpVT, VT);
40084008
else
4009-
CallOptions.setSExt(true);
4009+
CallOptions.setIsSigned(true); // FIXME: Is this needed?
40104010
std::pair<SDValue, SDValue> Tmp = TLI.makeLibCall(DAG, LC, VT, Op,
40114011
CallOptions, dl, Chain);
40124012
SplitInteger(Tmp.first, Lo, Hi);
@@ -4098,7 +4098,7 @@ void DAGTypeLegalizer::ExpandIntRes_XROUND_XRINT(SDNode *N, SDValue &Lo,
40984098
EVT RetVT = N->getValueType(0);
40994099

41004100
TargetLowering::MakeLibCallOptions CallOptions;
4101-
CallOptions.setSExt(true);
4101+
CallOptions.setIsSigned(true);
41024102
std::pair<SDValue, SDValue> Tmp = TLI.makeLibCall(DAG, LC, RetVT,
41034103
Op, CallOptions, dl,
41044104
Chain);
@@ -4269,7 +4269,7 @@ void DAGTypeLegalizer::ExpandIntRes_MUL(SDNode *N,
42694269
// upper half of the result if it exceeds VT.
42704270
SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
42714271
TargetLowering::MakeLibCallOptions CallOptions;
4272-
CallOptions.setSExt(true);
4272+
CallOptions.setIsSigned(true);
42734273
SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, CallOptions, dl).first,
42744274
Lo, Hi);
42754275
}
@@ -4640,7 +4640,7 @@ void DAGTypeLegalizer::ExpandIntRes_SDIV(SDNode *N,
46404640
assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!");
46414641

46424642
TargetLowering::MakeLibCallOptions CallOptions;
4643-
CallOptions.setSExt(true);
4643+
CallOptions.setIsSigned(true);
46444644
SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, CallOptions, dl).first, Lo, Hi);
46454645
}
46464646

@@ -4880,7 +4880,7 @@ void DAGTypeLegalizer::ExpandIntRes_Shift(SDNode *N,
48804880
SDValue ShAmt = DAG.getZExtOrTrunc(N->getOperand(1), dl, ShAmtTy);
48814881
SDValue Ops[2] = {N->getOperand(0), ShAmt};
48824882
TargetLowering::MakeLibCallOptions CallOptions;
4883-
CallOptions.setSExt(isSigned);
4883+
CallOptions.setIsSigned(isSigned);
48844884
SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, CallOptions, dl).first, Lo, Hi);
48854885
return;
48864886
}
@@ -4970,7 +4970,7 @@ void DAGTypeLegalizer::ExpandIntRes_SREM(SDNode *N,
49704970
assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!");
49714971

49724972
TargetLowering::MakeLibCallOptions CallOptions;
4973-
CallOptions.setSExt(true);
4973+
CallOptions.setIsSigned(true);
49744974
SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, CallOptions, dl).first, Lo, Hi);
49754975
}
49764976

@@ -5659,7 +5659,7 @@ SDValue DAGTypeLegalizer::ExpandIntOp_XINT_TO_FP(SDNode *N) {
56595659
assert(LC != RTLIB::UNKNOWN_LIBCALL &&
56605660
"Don't know how to expand this XINT_TO_FP!");
56615661
TargetLowering::MakeLibCallOptions CallOptions;
5662-
CallOptions.setSExt(true);
5662+
CallOptions.setIsSigned(true);
56635663
std::pair<SDValue, SDValue> Tmp =
56645664
TLI.makeLibCall(DAG, LC, DstVT, Op, CallOptions, SDLoc(N), Chain);
56655665

‎llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -160,7 +160,7 @@ TargetLowering::makeLibCall(SelectionDAG &DAG, RTLIB::Libcall LC, EVT RetVT,
160160
Entry.Node = NewOp;
161161
Entry.Ty = Entry.Node.getValueType().getTypeForEVT(*DAG.getContext());
162162
Entry.IsSExt = shouldSignExtendTypeInLibCall(NewOp.getValueType(),
163-
CallOptions.IsSExt);
163+
CallOptions.IsSigned);
164164
Entry.IsZExt = !Entry.IsSExt;
165165

166166
if (CallOptions.IsSoften &&
@@ -177,7 +177,7 @@ TargetLowering::makeLibCall(SelectionDAG &DAG, RTLIB::Libcall LC, EVT RetVT,
177177

178178
Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
179179
TargetLowering::CallLoweringInfo CLI(DAG);
180-
bool signExtend = shouldSignExtendTypeInLibCall(RetVT, CallOptions.IsSExt);
180+
bool signExtend = shouldSignExtendTypeInLibCall(RetVT, CallOptions.IsSigned);
181181
bool zeroExtend = !signExtend;
182182

183183
if (CallOptions.IsSoften &&
@@ -10876,7 +10876,7 @@ void TargetLowering::forceExpandWideMUL(SelectionDAG &DAG, const SDLoc &dl,
1087610876
// Attempt a libcall.
1087710877
SDValue Ret;
1087810878
TargetLowering::MakeLibCallOptions CallOptions;
10879-
CallOptions.setSExt(Signed);
10879+
CallOptions.setIsSigned(Signed);
1088010880
CallOptions.setIsPostTypeLegalization(true);
1088110881
if (shouldSplitFunctionArgumentsAsLittleEndian(DAG.getDataLayout())) {
1088210882
// Halves of WideVT are packed into registers in different order

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