[DAG] Applied formatting

Author: GrumpyPigSkin

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

@@ -9772,9 +9772,10 @@ SDValue DAGCombiner::MatchLoadCombine(SDNode *N) {
                           MemVT))
     return SDValue();
 
-  auto IsRotateLoaded = [](
-      ArrayRef<int64_t> ByteOffsets, int64_t FirstOffset, unsigned BitWidth) {
-    // Ensure that we have the correct width type, we want to combine two 32 loads into a 64 bit load.
+  auto IsRotateLoaded = [](ArrayRef<int64_t> ByteOffsets, int64_t FirstOffset,
+                           unsigned BitWidth) {
+    // Ensure that we have the correct width type, we want to combine two 32
+    // loads into a 64 bit load.
     if (BitWidth != 64 || ByteOffsets.size() != 8)
       return false;
 
@@ -9795,13 +9796,13 @@ SDValue DAGCombiner::MatchLoadCombine(SDNode *N) {
   // little endian value load
   std::optional<bool> IsBigEndian = isBigEndian(
       ArrayRef(ByteOffsets).drop_back(ZeroExtendedBytes), FirstOffset);
-  
+
   bool IsRotated = false;
   if (!IsBigEndian) {
     IsRotated =
-          IsRotateLoaded(ArrayRef(ByteOffsets).drop_back(ZeroExtendedBytes),
-                         FirstOffset, VT.getSizeInBits());
-    
+        IsRotateLoaded(ArrayRef(ByteOffsets).drop_back(ZeroExtendedBytes),
+                       FirstOffset, VT.getSizeInBits());
+
     if (!IsRotated)
       return SDValue();
   }

llvm/test/CodeGen/X86/dagcombine-bswap-to-rotate.ll

@@ -10,8 +10,6 @@ define i64 @test_load_bswap_to_rotate(ptr %p) {
 ; CHECK-NEXT:    movq (%rdi), %rax
 ; CHECK-NEXT:    rorq $32, %rax
 ; CHECK-NEXT:    retq
-;
-; CHECK-NOT: movl
 
   %p.hi = getelementptr inbounds nuw i8, ptr %p, i64 4
   %lo = load i32, ptr %p