[RISCV] Fix Lsb > Msb case in (sra (sext_inreg X, _), C) for th.ext

According the spec
https://github.com/XUANTIE-RV/thead-extension-spec/releases/tag/2.3.0,
the operation of `th.ext rd, rs1, msb, lsb` is

  reg[rd] := sign_extend(reg[rs1][msb:lsb])

The spec doesn't specify if lsb is greater than msb.

I don't think lsb can be greater than msb. So that If
the shift-right amount is greater than msb, we can set lsb equal to
msb to extract the bit rs1[msb] and sign-extend it.

Author: tclin914

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

@@ -653,7 +653,9 @@ bool RISCVDAGToDAGISel::trySignedBitfieldExtract(SDNode *Node) {
       return false;
 
     const unsigned Msb = ExtSize - 1;
-    const unsigned Lsb = RightShAmt;
+    // If the shift-right amount is greater than Msb, it means that extracts
+    // the X[Msb] bit and sign-extend it.
+    const unsigned Lsb = RightShAmt > Msb ? Msb : RightShAmt;
 
     SDNode *TH_EXT = BitfieldExtract(N0, Msb, Lsb, DL, VT);
     ReplaceNode(Node, TH_EXT);

llvm/test/CodeGen/RISCV/rv32xtheadbb.ll

@@ -426,7 +426,7 @@ define i32 @sext_sextinreg_sra_2(i16 %a) nounwind {
 ;
 ; RV32XTHEADBB-LABEL: sext_sextinreg_sra_2:
 ; RV32XTHEADBB:       # %bb.0:
-; RV32XTHEADBB-NEXT:    th.ext a0, a0, 15, 24
+; RV32XTHEADBB-NEXT:    th.ext a0, a0, 15, 15
 ; RV32XTHEADBB-NEXT:    ret
   %sext = sext i16 %a to i32
   %shr = ashr exact i32 %sext, 24