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[RISCV] Expand bf16 FNEG/FABS/FCOPYSIGN (#108245)
The motivation for this is to start promoting bf16 ops to f32 so that we can mark bf16 as a supported type in RISCVTTIImpl::isElementTypeLegalForScalableVector and scalably-vectorize it. This starts with expanding the nodes that can't be promoted to f32 due to canonicalizing NaNs, similarly to f16 in #106652.
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‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp

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@@ -1118,6 +1118,11 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
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if (Subtarget.hasStdExtZfbfmin())
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setOperationAction(ISD::SPLAT_VECTOR, VT, Custom);
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setOperationAction({ISD::LOAD, ISD::STORE}, VT, Custom);
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setOperationAction(ISD::FNEG, VT, Expand);
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setOperationAction(ISD::FABS, VT, Expand);
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setOperationAction(ISD::FCOPYSIGN, VT, Expand);
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// TODO: Promote to fp32.
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}
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}

‎llvm/test/CodeGen/RISCV/rvv/vfabs-sdnode-bf16.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc < %s -mtriple=riscv32 -mattr=+v,+zvfbfmin -verify-machineinstrs | FileCheck %s
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; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+zvfbfmin -verify-machineinstrs | FileCheck %s
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define <vscale x 1 x bfloat> @nxv1bf16(<vscale x 1 x bfloat> %v) {
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; CHECK-LABEL: nxv1bf16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lui a0, 8
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; CHECK-NEXT: addi a0, a0, -1
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; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
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; CHECK-NEXT: vand.vx v8, v8, a0
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; CHECK-NEXT: ret
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%r = call <vscale x 1 x bfloat> @llvm.fabs.nxv1bf16(<vscale x 1 x bfloat> %v)
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ret <vscale x 1 x bfloat> %r
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}
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define <vscale x 2 x bfloat> @nxv2bf16(<vscale x 2 x bfloat> %v) {
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; CHECK-LABEL: nxv2bf16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lui a0, 8
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; CHECK-NEXT: addi a0, a0, -1
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; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
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; CHECK-NEXT: vand.vx v8, v8, a0
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; CHECK-NEXT: ret
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%r = call <vscale x 2 x bfloat> @llvm.fabs.nxv2bf16(<vscale x 2 x bfloat> %v)
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ret <vscale x 2 x bfloat> %r
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}
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define <vscale x 4 x bfloat> @nxv4bf16(<vscale x 4 x bfloat> %v) {
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; CHECK-LABEL: nxv4bf16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lui a0, 8
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; CHECK-NEXT: addi a0, a0, -1
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; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
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; CHECK-NEXT: vand.vx v8, v8, a0
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; CHECK-NEXT: ret
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%r = call <vscale x 4 x bfloat> @llvm.fabs.nxv4bf16(<vscale x 4 x bfloat> %v)
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ret <vscale x 4 x bfloat> %r
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}
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define <vscale x 8 x bfloat> @nxv8bf16(<vscale x 8 x bfloat> %v) {
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; CHECK-LABEL: nxv8bf16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lui a0, 8
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; CHECK-NEXT: addi a0, a0, -1
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; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma
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; CHECK-NEXT: vand.vx v8, v8, a0
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; CHECK-NEXT: ret
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%r = call <vscale x 8 x bfloat> @llvm.fabs.nxv8bf16(<vscale x 8 x bfloat> %v)
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ret <vscale x 8 x bfloat> %r
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}
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define <vscale x 16 x bfloat> @nxv16bf16(<vscale x 16 x bfloat> %v) {
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; CHECK-LABEL: nxv16bf16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lui a0, 8
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; CHECK-NEXT: addi a0, a0, -1
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; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, ma
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; CHECK-NEXT: vand.vx v8, v8, a0
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; CHECK-NEXT: ret
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%r = call <vscale x 16 x bfloat> @llvm.fabs.nxv16bf16(<vscale x 16 x bfloat> %v)
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ret <vscale x 16 x bfloat> %r
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}
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define <vscale x 32 x bfloat> @nxv32bf16(<vscale x 32 x bfloat> %v) {
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; CHECK-LABEL: nxv32bf16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lui a0, 8
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; CHECK-NEXT: addi a0, a0, -1
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; CHECK-NEXT: vsetvli a1, zero, e16, m8, ta, ma
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; CHECK-NEXT: vand.vx v8, v8, a0
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; CHECK-NEXT: ret
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%r = call <vscale x 32 x bfloat> @llvm.fabs.nxv32bf16(<vscale x 32 x bfloat> %v)
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ret <vscale x 32 x bfloat> %r
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}

‎llvm/test/CodeGen/RISCV/rvv/vfcopysign-sdnode-bf16.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc < %s -mtriple=riscv32 -mattr=+v,+zvfbfmin -verify-machineinstrs | FileCheck %s
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; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+zvfbfmin -verify-machineinstrs | FileCheck %s
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define <vscale x 1 x bfloat> @nxv1bf16(<vscale x 1 x bfloat> %vm, <vscale x 1 x bfloat> %vs) {
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; CHECK-LABEL: nxv1bf16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lui a0, 8
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; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
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; CHECK-NEXT: vand.vx v9, v9, a0
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; CHECK-NEXT: addi a0, a0, -1
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; CHECK-NEXT: vand.vx v8, v8, a0
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; CHECK-NEXT: vor.vv v8, v8, v9
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; CHECK-NEXT: ret
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%r = call <vscale x 1 x bfloat> @llvm.copysign.nxv1bf16(<vscale x 1 x bfloat> %vm, <vscale x 1 x bfloat> %vs)
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ret <vscale x 1 x bfloat> %r
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}
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define <vscale x 2 x bfloat> @nxv2bf16(<vscale x 2 x bfloat> %vm, <vscale x 2 x bfloat> %vs) {
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; CHECK-LABEL: nxv2bf16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lui a0, 8
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; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
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; CHECK-NEXT: vand.vx v9, v9, a0
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; CHECK-NEXT: addi a0, a0, -1
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; CHECK-NEXT: vand.vx v8, v8, a0
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; CHECK-NEXT: vor.vv v8, v8, v9
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; CHECK-NEXT: ret
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%r = call <vscale x 2 x bfloat> @llvm.copysign.nxv2bf16(<vscale x 2 x bfloat> %vm, <vscale x 2 x bfloat> %vs)
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ret <vscale x 2 x bfloat> %r
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}
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define <vscale x 4 x bfloat> @nxv4bf16(<vscale x 4 x bfloat> %vm, <vscale x 4 x bfloat> %vs) {
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; CHECK-LABEL: nxv4bf16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lui a0, 8
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; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
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; CHECK-NEXT: vand.vx v9, v9, a0
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; CHECK-NEXT: addi a0, a0, -1
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; CHECK-NEXT: vand.vx v8, v8, a0
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; CHECK-NEXT: vor.vv v8, v8, v9
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; CHECK-NEXT: ret
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%r = call <vscale x 4 x bfloat> @llvm.copysign.nxv4bf16(<vscale x 4 x bfloat> %vm, <vscale x 4 x bfloat> %vs)
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ret <vscale x 4 x bfloat> %r
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}
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define <vscale x 8 x bfloat> @nxv8bf16(<vscale x 8 x bfloat> %vm, <vscale x 8 x bfloat> %vs) {
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; CHECK-LABEL: nxv8bf16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lui a0, 8
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; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma
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; CHECK-NEXT: vand.vx v10, v10, a0
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; CHECK-NEXT: addi a0, a0, -1
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; CHECK-NEXT: vand.vx v8, v8, a0
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; CHECK-NEXT: vor.vv v8, v8, v10
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; CHECK-NEXT: ret
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%r = call <vscale x 8 x bfloat> @llvm.copysign.nxv8bf16(<vscale x 8 x bfloat> %vm, <vscale x 8 x bfloat> %vs)
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ret <vscale x 8 x bfloat> %r
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}
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define <vscale x 16 x bfloat> @nxv16bf16(<vscale x 16 x bfloat> %vm, <vscale x 16 x bfloat> %vs) {
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; CHECK-LABEL: nxv16bf16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lui a0, 8
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; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, ma
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; CHECK-NEXT: vand.vx v12, v12, a0
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; CHECK-NEXT: addi a0, a0, -1
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; CHECK-NEXT: vand.vx v8, v8, a0
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; CHECK-NEXT: vor.vv v8, v8, v12
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; CHECK-NEXT: ret
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%r = call <vscale x 16 x bfloat> @llvm.copysign.nxv16bf16(<vscale x 16 x bfloat> %vm, <vscale x 16 x bfloat> %vs)
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ret <vscale x 16 x bfloat> %r
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}
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define <vscale x 32 x bfloat> @nxv32bf32(<vscale x 32 x bfloat> %vm, <vscale x 32 x bfloat> %vs) {
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; CHECK-LABEL: nxv32bf32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lui a0, 8
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; CHECK-NEXT: vsetvli a1, zero, e16, m8, ta, ma
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; CHECK-NEXT: vand.vx v16, v16, a0
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; CHECK-NEXT: addi a0, a0, -1
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; CHECK-NEXT: vand.vx v8, v8, a0
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; CHECK-NEXT: vor.vv v8, v8, v16
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; CHECK-NEXT: ret
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%r = call <vscale x 32 x bfloat> @llvm.copysign.nxv32bf32(<vscale x 32 x bfloat> %vm, <vscale x 32 x bfloat> %vs)
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ret <vscale x 32 x bfloat> %r
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}

‎llvm/test/CodeGen/RISCV/rvv/vfneg-sdnode-bf16.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc < %s -mtriple=riscv32 -mattr=+v,+zvfbfmin -verify-machineinstrs | FileCheck %s
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; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+zvfbfmin -verify-machineinstrs | FileCheck %s
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define <vscale x 1 x bfloat> @nxv1bf16(<vscale x 1 x bfloat> %va) {
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; CHECK-LABEL: nxv1bf16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lui a0, 8
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; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
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; CHECK-NEXT: vxor.vx v8, v8, a0
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; CHECK-NEXT: ret
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%vb = fneg <vscale x 1 x bfloat> %va
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ret <vscale x 1 x bfloat> %vb
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}
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define <vscale x 2 x bfloat> @nxv2bf16(<vscale x 2 x bfloat> %va) {
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; CHECK-LABEL: nxv2bf16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lui a0, 8
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; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
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; CHECK-NEXT: vxor.vx v8, v8, a0
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; CHECK-NEXT: ret
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%vb = fneg <vscale x 2 x bfloat> %va
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ret <vscale x 2 x bfloat> %vb
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}
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define <vscale x 4 x bfloat> @nxv4bf16(<vscale x 4 x bfloat> %va) {
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; CHECK-LABEL: nxv4bf16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lui a0, 8
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; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
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; CHECK-NEXT: vxor.vx v8, v8, a0
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; CHECK-NEXT: ret
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%vb = fneg <vscale x 4 x bfloat> %va
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ret <vscale x 4 x bfloat> %vb
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}
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define <vscale x 8 x bfloat> @nxv8bf16(<vscale x 8 x bfloat> %va) {
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; CHECK-LABEL: nxv8bf16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lui a0, 8
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; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma
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; CHECK-NEXT: vxor.vx v8, v8, a0
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; CHECK-NEXT: ret
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%vb = fneg <vscale x 8 x bfloat> %va
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ret <vscale x 8 x bfloat> %vb
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}
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define <vscale x 16 x bfloat> @nxv16bf16(<vscale x 16 x bfloat> %va) {
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; CHECK-LABEL: nxv16bf16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lui a0, 8
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; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, ma
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; CHECK-NEXT: vxor.vx v8, v8, a0
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; CHECK-NEXT: ret
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%vb = fneg <vscale x 16 x bfloat> %va
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ret <vscale x 16 x bfloat> %vb
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}
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define <vscale x 32 x bfloat> @nxv32bf16(<vscale x 32 x bfloat> %va) {
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; CHECK-LABEL: nxv32bf16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lui a0, 8
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; CHECK-NEXT: vsetvli a1, zero, e16, m8, ta, ma
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; CHECK-NEXT: vxor.vx v8, v8, a0
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; CHECK-NEXT: ret
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%vb = fneg <vscale x 32 x bfloat> %va
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ret <vscale x 32 x bfloat> %vb
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}

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