fixup! Add combines_for_extload to RISCVPostLegalizerCombiner.

Author: topperc

llvm/lib/Target/RISCV/RISCVCombine.td

@@ -23,6 +23,6 @@ def RISCVO0PreLegalizerCombiner: GICombiner<
 // TODO: Add more combines.
 def RISCVPostLegalizerCombiner
     : GICombiner<"RISCVPostLegalizerCombinerImpl",
-                 [redundant_and, identity_combines, commute_constant_to_rhs,
-                  constant_fold_cast_op]> {
+                 [combines_for_extload, redundant_and, identity_combines,
+                  commute_constant_to_rhs, constant_fold_cast_op]> {
 }

llvm/test/CodeGen/RISCV/GlobalISel/double-convert.ll

@@ -106,9 +106,7 @@ define double @fcvt_d_wu_load(ptr %p) nounwind {
 ;
 ; RV64IFD-LABEL: fcvt_d_wu_load:
 ; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    lw a0, 0(a0)
-; RV64IFD-NEXT:    slli a0, a0, 32
-; RV64IFD-NEXT:    srli a0, a0, 32
+; RV64IFD-NEXT:    lwu a0, 0(a0)
 ; RV64IFD-NEXT:    fcvt.d.wu fa0, a0
 ; RV64IFD-NEXT:    ret
   %a = load i32, ptr %p

llvm/test/CodeGen/RISCV/GlobalISel/float-convert.ll

@@ -109,9 +109,7 @@ define float @fcvt_s_wu_load(ptr %p) nounwind {
 ;
 ; RV64IF-LABEL: fcvt_s_wu_load:
 ; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    lw a0, 0(a0)
-; RV64IF-NEXT:    slli a0, a0, 32
-; RV64IF-NEXT:    srli a0, a0, 32
+; RV64IF-NEXT:    lwu a0, 0(a0)
 ; RV64IF-NEXT:    fcvt.s.wu fa0, a0
 ; RV64IF-NEXT:    ret
   %a = load i32, ptr %p