Skip to content

Commit cbed865

Browse files
committed
[GlobalISel][IRTranslator] Ignore the llvm.experimental.noalias.scope.decl intrinsic.
These don't generate any code.
1 parent 810572c commit cbed865

File tree

2 files changed

+15
-0
lines changed

2 files changed

+15
-0
lines changed

llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2126,6 +2126,7 @@ bool IRTranslator::translateKnownIntrinsic(const CallInst &CI, Intrinsic::ID ID,
21262126
return true;
21272127
}
21282128
case Intrinsic::assume:
2129+
case Intrinsic::experimental_noalias_scope_decl:
21292130
case Intrinsic::var_annotation:
21302131
case Intrinsic::sideeffect:
21312132
// Discard annotate attributes, assumptions, and artificial side-effects.

llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll

Lines changed: 14 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2388,6 +2388,20 @@ define void @test_assume(i1 %x) {
23882388
ret void
23892389
}
23902390

2391+
declare void @llvm.experimental.noalias.scope.decl(metadata)
2392+
define void @test.llvm.noalias.scope.decl(i8* %P, i8* %Q) nounwind ssp {
2393+
tail call void @llvm.experimental.noalias.scope.decl(metadata !3)
2394+
; CHECK-LABEL: name: test.llvm.noalias.scope.decl
2395+
; CHECK-NOT: llvm.experimental.noalias.scope.decl
2396+
; CHECK: RET_ReallyLR
2397+
ret void
2398+
}
2399+
2400+
!3 = !{ !4 }
2401+
!4 = distinct !{ !4, !5, !"test1: var" }
2402+
!5 = distinct !{ !5, !"test1" }
2403+
2404+
23912405
declare void @llvm.sideeffect()
23922406
define void @test_sideeffect() {
23932407
; CHECK-LABEL: name: test_sideeffect

0 commit comments

Comments
 (0)