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fixup! address review comment
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llvm/docs/LangRef.rst

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@@ -24003,7 +24003,7 @@ second return value must be at least 1, even if the first lane is masked-off.
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The second result is usually less than ``evl`` when an exception would occur
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for reading that lane, but it can be reduced for any reason. This facilitates
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emulating this intrinsic when the hardware has only supports narrower vector
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emulating this intrinsic when the hardware only supports narrower vector
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types natively or when when hardware does not support fault-only-first loads.
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Masked-on lanes that are not inbounds of the allocation that contains the first

llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

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@@ -8483,13 +8483,12 @@ void SelectionDAGBuilder::visitVPLoadFF(
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AAMDNodes AAInfo = VPIntrin.getAAMetadata();
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const MDNode *Ranges = VPIntrin.getMetadata(LLVMContext::MD_range);
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SDValue LD;
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bool AddToChain = true;
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// Do not serialize variable-length loads of constant memory with
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// anything.
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if (!Alignment)
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Alignment = DAG.getEVTAlign(VT);
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MemoryLocation ML = MemoryLocation::getAfter(PtrOperand, AAInfo);
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AddToChain = !BatchAA || !BatchAA->pointsToConstantMemory(ML);
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bool AddToChain = !BatchAA || !BatchAA->pointsToConstantMemory(ML);
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SDValue InChain = AddToChain ? DAG.getRoot() : DAG.getEntryNode();
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MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
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MachinePointerInfo(PtrOperand), MachineMemOperand::MOLoad,

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