Skip to content

Commit cc48332

Browse files
MaskRayMaskRay
committed
[𝘀𝗽𝗿] initial version
Created using spr 1.3.5-bogner
1 parent 77410f2 commit cc48332

File tree

10 files changed

+141
-55
lines changed

10 files changed

+141
-55
lines changed

‎llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp‎

Lines changed: 12 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1311,11 +1311,21 @@ class MipsOperand : public MCParsedAsmOperand {
13111311
}
13121312

13131313
template <unsigned Bits> bool isSImm() const {
1314-
return isConstantImm() ? isInt<Bits>(getConstantImm()) : isImm();
1314+
if (!isImm())
1315+
return false;
1316+
int64_t Res;
1317+
if (getImm()->evaluateAsAbsolute(Res))
1318+
return isInt<Bits>(Res);
1319+
return true;
13151320
}
13161321

13171322
template <unsigned Bits> bool isUImm() const {
1318-
return isConstantImm() ? isUInt<Bits>(getConstantImm()) : isImm();
1323+
if (!isImm())
1324+
return false;
1325+
int64_t Res;
1326+
if (getImm()->evaluateAsAbsolute(Res))
1327+
return isUInt<Bits>(Res);
1328+
return true;
13191329
}
13201330

13211331
template <unsigned Bits> bool isAnyImm() const {

‎llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp‎

Lines changed: 19 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -60,6 +60,11 @@ static unsigned adjustFixupValue(const MCFixup &Fixup, uint64_t Value,
6060
case Mips::fixup_MIPS_PCLO16:
6161
Value &= 0xffff;
6262
break;
63+
case Mips::fixup_Mips_AnyImm16:
64+
if (!isInt<16>(Value) && !isUInt<16>(Value))
65+
Ctx.reportError(Fixup.getLoc(),
66+
"fixup value out of range [-32768, 65535]");
67+
break;
6368
case FK_DTPRel_4:
6469
case FK_DTPRel_8:
6570
case FK_TPRel_4:
@@ -351,16 +356,18 @@ std::optional<MCFixupKind> MipsAsmBackend::getFixupKind(StringRef Name) const {
351356
const MCFixupKindInfo &MipsAsmBackend::
352357
getFixupKindInfo(MCFixupKind Kind) const {
353358
const static MCFixupKindInfo LittleEndianInfos[] = {
354-
// This table *must* be in same the order of fixup_* kinds in
355-
// MipsFixupKinds.h.
356-
//
357-
// name offset bits flags
359+
// This table *must* be in same the order of fixup_* kinds in
360+
// MipsFixupKinds.h.
361+
//
362+
// name offset bits flags
363+
// clang-format off
358364
{ "fixup_Mips_16", 0, 16, 0 },
359365
{ "fixup_Mips_32", 0, 32, 0 },
360366
{ "fixup_Mips_REL32", 0, 32, 0 },
361367
{ "fixup_Mips_26", 0, 26, 0 },
362368
{ "fixup_Mips_HI16", 0, 16, 0 },
363369
{ "fixup_Mips_LO16", 0, 16, 0 },
370+
{ "fixup_Mips_AnyImm16", 0, 16, 0 },
364371
{ "fixup_Mips_GPREL16", 0, 16, 0 },
365372
{ "fixup_Mips_LITERAL", 0, 16, 0 },
366373
{ "fixup_Mips_GOT", 0, 16, 0 },
@@ -424,22 +431,24 @@ getFixupKindInfo(MCFixupKind Kind) const {
424431
{ "fixup_Mips_SUB", 0, 64, 0 },
425432
{ "fixup_MICROMIPS_SUB", 0, 64, 0 },
426433
{ "fixup_Mips_JALR", 0, 32, 0 },
427-
{ "fixup_MICROMIPS_JALR", 0, 32, 0 }
434+
{ "fixup_MICROMIPS_JALR", 0, 32, 0 } // clang-format on
428435
};
429436
static_assert(std::size(LittleEndianInfos) == Mips::NumTargetFixupKinds,
430437
"Not all MIPS little endian fixup kinds added!");
431438

432439
const static MCFixupKindInfo BigEndianInfos[] = {
433-
// This table *must* be in same the order of fixup_* kinds in
434-
// MipsFixupKinds.h.
435-
//
436-
// name offset bits flags
440+
// This table *must* be in same the order of fixup_* kinds in
441+
// MipsFixupKinds.h.
442+
//
443+
// name offset bits flags
444+
// clang-format off
437445
{ "fixup_Mips_16", 16, 16, 0 },
438446
{ "fixup_Mips_32", 0, 32, 0 },
439447
{ "fixup_Mips_REL32", 0, 32, 0 },
440448
{ "fixup_Mips_26", 6, 26, 0 },
441449
{ "fixup_Mips_HI16", 16, 16, 0 },
442450
{ "fixup_Mips_LO16", 16, 16, 0 },
451+
{ "fixup_Mips_AnyImm16", 16, 16, 0 },
443452
{ "fixup_Mips_GPREL16", 16, 16, 0 },
444453
{ "fixup_Mips_LITERAL", 16, 16, 0 },
445454
{ "fixup_Mips_GOT", 16, 16, 0 },
@@ -503,7 +512,7 @@ getFixupKindInfo(MCFixupKind Kind) const {
503512
{ "fixup_Mips_SUB", 0, 64, 0 },
504513
{ "fixup_MICROMIPS_SUB", 0, 64, 0 },
505514
{ "fixup_Mips_JALR", 0, 32, 0 },
506-
{ "fixup_MICROMIPS_JALR", 0, 32, 0 }
515+
{ "fixup_MICROMIPS_JALR", 0, 32, 0 } // clang-format on
507516
};
508517
static_assert(std::size(BigEndianInfos) == Mips::NumTargetFixupKinds,
509518
"Not all MIPS big endian fixup kinds added!");

‎llvm/lib/Target/Mips/MCTargetDesc/MipsBaseInfo.h‎

Lines changed: 14 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -26,7 +26,8 @@ namespace llvm {
2626
/// instruction info tracks.
2727
///
2828
namespace MipsII {
29-
/// Target Operand Flag enum.
29+
/// Target Operand Flag enum.
30+
// clang-format off
3031
enum TOF {
3132
//===------------------------------------------------------------------===//
3233
// Mips Specific MachineOperand flags.
@@ -100,7 +101,7 @@ namespace MipsII {
100101
MO_DLLIMPORT = 0x20,
101102
};
102103

103-
enum {
104+
enum {
104105
//===------------------------------------------------------------------===//
105106
// Instruction encodings. These are the standard/most common forms for
106107
// Mips instructions.
@@ -132,13 +133,18 @@ namespace MipsII {
132133
/// HasFCCRegOperand - Instruction uses an $fcc<x> register.
133134
HasFCCRegOperand = 1 << 6
134135

135-
};
136+
};
137+
// clang-format on
136138

137-
enum OperandType : unsigned {
138-
OPERAND_FIRST_MIPS_MEM_IMM = MCOI::OPERAND_FIRST_TARGET,
139-
OPERAND_MEM_SIMM9 = OPERAND_FIRST_MIPS_MEM_IMM,
140-
OPERAND_LAST_MIPS_MEM_IMM = OPERAND_MEM_SIMM9
141-
};
139+
enum OperandType : unsigned {
140+
OPERAND_FIRST_MIPS_MEM_IMM = MCOI::OPERAND_FIRST_TARGET,
141+
OPERAND_MEM_SIMM9 = OPERAND_FIRST_MIPS_MEM_IMM,
142+
OPERAND_LAST_MIPS_MEM_IMM = OPERAND_MEM_SIMM9
143+
};
144+
145+
static inline unsigned getFormat(uint64_t TSFlags) {
146+
return TSFlags & FormMask;
147+
}
142148
}
143149

144150
inline static MCRegister getMSARegFromFReg(MCRegister Reg) {

‎llvm/lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -328,7 +328,8 @@ unsigned MipsELFObjectWriter::getRelocType(MCContext &Ctx,
328328
return ELF::R_MICROMIPS_JALR;
329329
}
330330

331-
llvm_unreachable("invalid fixup kind!");
331+
Ctx.reportError(Fixup.getLoc(), "unsupported relocation type");
332+
return ELF::R_MIPS_NONE;
332333
}
333334

334335
/// Sort relocation table entries by offset except where another order is

‎llvm/lib/Target/Mips/MCTargetDesc/MipsFixupKinds.h‎

Lines changed: 13 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -13,14 +13,15 @@
1313

1414
namespace llvm {
1515
namespace Mips {
16-
// Although most of the current fixup types reflect a unique relocation
17-
// one can have multiple fixup types for a given relocation and thus need
18-
// to be uniquely named.
19-
//
20-
// This table *must* be in the same order of
21-
// MCFixupKindInfo Infos[Mips::NumTargetFixupKinds]
22-
// in MipsAsmBackend.cpp.
23-
//
16+
// Although most of the current fixup types reflect a unique relocation
17+
// one can have multiple fixup types for a given relocation and thus need
18+
// to be uniquely named.
19+
//
20+
// This table *must* be in the same order of
21+
// MCFixupKindInfo Infos[Mips::NumTargetFixupKinds]
22+
// in MipsAsmBackend.cpp.
23+
//
24+
// clang-format off
2425
enum Fixups {
2526
// Branch fixups resulting in R_MIPS_16.
2627
fixup_Mips_16 = FirstTargetFixupKind,
@@ -40,6 +41,9 @@ namespace Mips {
4041
// Pure lower 16 bit fixup resulting in - R_MIPS_LO16.
4142
fixup_Mips_LO16,
4243

44+
// 16-bit fixup that must be resolved.
45+
fixup_Mips_AnyImm16,
46+
4347
// 16 bit fixup for GP offest resulting in - R_MIPS_GPREL16.
4448
fixup_Mips_GPREL16,
4549

@@ -226,6 +230,7 @@ namespace Mips {
226230
LastTargetFixupKind,
227231
NumTargetFixupKinds = LastTargetFixupKind - FirstTargetFixupKind
228232
};
233+
// clang-format on
229234
} // namespace Mips
230235
} // namespace llvm
231236

‎llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp‎

Lines changed: 24 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -11,6 +11,7 @@
1111
//===----------------------------------------------------------------------===//
1212

1313
#include "MipsMCCodeEmitter.h"
14+
#include "MCTargetDesc/MipsBaseInfo.h"
1415
#include "MCTargetDesc/MipsFixupKinds.h"
1516
#include "MCTargetDesc/MipsMCExpr.h"
1617
#include "MCTargetDesc/MipsMCTargetDesc.h"
@@ -578,23 +579,7 @@ getSImm9AddiuspValue(const MCInst &MI, unsigned OpNo,
578579
unsigned MipsMCCodeEmitter::
579580
getExprOpValue(const MCExpr *Expr, SmallVectorImpl<MCFixup> &Fixups,
580581
const MCSubtargetInfo &STI) const {
581-
int64_t Res;
582-
583-
if (Expr->evaluateAsAbsolute(Res))
584-
return Res;
585-
586582
MCExpr::ExprKind Kind = Expr->getKind();
587-
if (Kind == MCExpr::Constant) {
588-
return cast<MCConstantExpr>(Expr)->getValue();
589-
}
590-
591-
if (Kind == MCExpr::Binary) {
592-
unsigned Res =
593-
getExprOpValue(cast<MCBinaryExpr>(Expr)->getLHS(), Fixups, STI);
594-
Res += getExprOpValue(cast<MCBinaryExpr>(Expr)->getRHS(), Fixups, STI);
595-
return Res;
596-
}
597-
598583
if (Kind == MCExpr::Target) {
599584
const MipsMCExpr *MipsExpr = cast<MipsMCExpr>(Expr);
600585

@@ -712,8 +697,7 @@ getExprOpValue(const MCExpr *Expr, SmallVectorImpl<MCFixup> &Fixups,
712697
return 0;
713698
}
714699

715-
if (Kind == MCExpr::SymbolRef)
716-
Ctx.reportError(Expr->getLoc(), "expected an immediate");
700+
Ctx.reportError(Expr->getLoc(), "expected an immediate");
717701
return 0;
718702
}
719703

@@ -732,9 +716,29 @@ getMachineOpValue(const MCInst &MI, const MCOperand &MO,
732716
} else if (MO.isDFPImm()) {
733717
return static_cast<unsigned>(bit_cast<double>(MO.getDFPImm()));
734718
}
735-
// MO must be an Expr.
719+
// TODO: Set EncoderMethod to "getImmOpValue" for imm Operand so that
720+
// getMachineOpValue will not be called for isExpr code paths.
736721
assert(MO.isExpr());
737-
return getExprOpValue(MO.getExpr(),Fixups, STI);
722+
return getImmOpValue(MI, MO, Fixups, STI);
723+
}
724+
725+
unsigned MipsMCCodeEmitter::getImmOpValue(const MCInst &MI, const MCOperand &MO,
726+
SmallVectorImpl<MCFixup> &Fixups,
727+
const MCSubtargetInfo &STI) const {
728+
if (MO.isImm())
729+
return MO.getImm();
730+
assert(MO.isExpr() && "getImmOpValue expects only expressions or immediates");
731+
const MCExpr *Expr = MO.getExpr();
732+
int64_t Res;
733+
if (Expr->evaluateAsAbsolute(Res))
734+
return Res;
735+
unsigned MIFrm = MipsII::getFormat(MCII.get(MI.getOpcode()).TSFlags);
736+
if (!isa<MCTargetExpr>(Expr) && MIFrm == MipsII::FrmI) {
737+
Fixups.push_back(MCFixup::create(
738+
0, Expr, MCFixupKind(Mips::fixup_Mips_AnyImm16), MI.getLoc()));
739+
return 0;
740+
}
741+
return getExprOpValue(Expr, Fixups, STI);
738742
}
739743

740744
/// Return binary encoding of memory related operand.

‎llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -177,6 +177,9 @@ class MipsMCCodeEmitter : public MCCodeEmitter {
177177
unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO,
178178
SmallVectorImpl<MCFixup> &Fixups,
179179
const MCSubtargetInfo &STI) const;
180+
unsigned getImmOpValue(const MCInst &MI, const MCOperand &MO,
181+
SmallVectorImpl<MCFixup> &Fixups,
182+
const MCSubtargetInfo &STI) const;
180183

181184
unsigned getMSAMemEncoding(const MCInst &MI, unsigned OpNo,
182185
SmallVectorImpl<MCFixup> &Fixups,

‎llvm/test/MC/Mips/fixup-expr.s‎

Lines changed: 37 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,37 @@
1+
# RUN: llvm-mc -filetype=obj -triple=mips64 %s -o %t.be
2+
# RUN: llvm-objdump -d %t.be | FileCheck %s
3+
# RUN: llvm-mc -filetype=obj -triple=mips64el %s -o %t.le
4+
# RUN: llvm-objdump -d %t.le | FileCheck %s
5+
6+
# RUN: not llvm-mc -filetype=obj -triple=mips64el --defsym ERR=1 %s -o /dev/null 2>&1 | FileCheck %s --check-prefix=ERR
7+
8+
# CHECK: addiu $4, $5, -0x8000
9+
# CHECK-NEXT: addiu $4, $5, -0x1
10+
# CHECK-NEXT: addiu $4, $5, -0x8000
11+
# CHECK-NEXT: addiu $4, $5, 0x7fff
12+
# CHECK-NEXT: addiu $4, $5, -0x1
13+
addiu $4, $5, v_32769+1
14+
addiu $4, $5, v65535
15+
addiu $4, $5, .L0-.L1
16+
addiu $4, $5, .L2-.L1
17+
addiu $4, $5, .L2-.L0+0
18+
19+
.ifdef ERR
20+
# ERR: :[[#@LINE+1]]:1: error: fixup value out of range [-32768, 65535]
21+
addiu $4, $5, v_32769
22+
# ERR: :[[#@LINE+1]]:1: error: fixup value out of range [-32768, 65535]
23+
addiu $4, $5, v65535+1
24+
25+
# ERR: [[#@LINE+1]]:1: error: fixup value out of range [-32768, 65535]
26+
addiu $4, $5, .L2-.L0+1
27+
.endif
28+
29+
v_32769 = -32769
30+
v65535 = 65535
31+
32+
.section .rodata,"a"
33+
.L0:
34+
.space 32768
35+
.L1:
36+
.space 32767
37+
.L2:

‎llvm/test/MC/Mips/fixup-out-of-range.s‎

Lines changed: 13 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,13 @@
1+
# RUN: not llvm-mc -triple mips64 -filetype obj %s -o /dev/null 2>&1 | FileCheck %s --implicit-check-not=error:
2+
3+
# CHECK: :[[#@LINE+1]]:1: error: fixup value out of range [-32768, 65535]
4+
addiu $t2, $t3, v_32769
5+
addiu $t2, $t3, v_32768
6+
addiu $t2, $t3, v65535
7+
# CHECK: :[[#@LINE+1]]:1: error: fixup value out of range [-32768, 65535]
8+
addiu $t2, $t3, v65536
9+
10+
v_32769 = -32769
11+
v_32768 = -32768
12+
v65535 = 65535
13+
v65536 = 65536

‎llvm/test/MC/Mips/imm-operand-err.s‎

Lines changed: 4 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1,15 +1,13 @@
11
## Print an error if a non-immediate operand is used while an immediate is expected
2-
# RUN: not llvm-mc -filetype=obj -triple=mips -o /dev/null %s 2>&1 | FileCheck %s
3-
# RUN: not llvm-mc -filetype=obj -triple=mips64 -o /dev/null %s 2>&1 | FileCheck %s
2+
# RUN: not llvm-mc -filetype=obj -triple=mips -o /dev/null %s 2>&1 | FileCheck %s --implicit-check-not=error:
3+
# RUN: not llvm-mc -filetype=obj -triple=mips64 -o /dev/null %s 2>&1 | FileCheck %s --implicit-check-not=error:
44

5-
# CHECK: [[#@LINE+1]]:16: error: expected an immediate
5+
# CHECK: [[#@LINE+1]]:3: error: unsupported relocation type
66
ori $4, $4, start
7-
# CHECK: [[#@LINE+1]]:17: error: expected an immediate
87
ori $4, $4, (start - .)
98

10-
# CHECK: [[#@LINE+1]]:18: error: expected an immediate
9+
# CHECK: [[#@LINE+1]]:3: error: unsupported relocation type
1110
addiu $4, $4, start
12-
# CHECK: [[#@LINE+1]]:19: error: expected an immediate
1311
addiu $4, $4, (start - .)
1412

1513
start:

0 commit comments

Comments
 (0)