[AArch64] fall back to SDAG for instructions with emulated TLS variables (#129215)

Fixes #126200 
At the moment, GlobalISel is missing an implementation for emulated TLS
variables.
I fixed the issue by falling back to SDAG in this case, as I currently
don't have the knowledge to implement it myself.

Co-authored-by: Schaller, Sebastian <[email protected]>

Author: sschaller

llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp

@@ -2960,8 +2960,12 @@ bool AArch64InstructionSelector::select(MachineInstr &I) {
       assert(OpFlags == AArch64II::MO_GOT);
     } else {
       GV = I.getOperand(1).getGlobal();
-      if (GV->isThreadLocal())
+      if (GV->isThreadLocal()) {
+        // We don't support instructions with emulated TLS variables yet
+        if (TM.useEmulatedTLS())
+          return false;
         return selectTLSGlobalValue(I, MRI);
+      }
       OpFlags = STI.ClassifyGlobalReference(GV, TM);
     }
 

llvm/test/CodeGen/AArch64/GlobalISel/emutls-fallback.ll

@@ -0,0 +1,29 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -emulated-tls -mtriple aarch64-apple-darwin -global-isel -global-isel-abort=2 %s -o - 2>&1 | FileCheck %s
+
+; This file checks that the fallback path for instructions with emulated TLS variables to selection dag works.
+
+; CHECK:        warning: Instruction selection used fallback path for main
+
+@x = thread_local global i32 42, align 4
+
+define i32 @main(i32 %argc, ptr %argv) {
+; CHECK-LABEL: main:
+; CHECK:       ; %bb.0: ; %entry
+; CHECK-NEXT:    stp x29, x30, [sp, #-16]! ; 16-byte Folded Spill
+; CHECK-NEXT:    .cfi_def_cfa_offset 16
+; CHECK-NEXT:    .cfi_offset w30, -8
+; CHECK-NEXT:    .cfi_offset w29, -16
+; CHECK-NEXT:  Lloh0:
+; CHECK-NEXT:    adrp x0, ___emutls_v.x@PAGE
+; CHECK-NEXT:  Lloh1:
+; CHECK-NEXT:    add x0, x0, ___emutls_v.x@PAGEOFF
+; CHECK-NEXT:    bl ___emutls_get_address
+; CHECK-NEXT:    ldr w0, [x0]
+; CHECK-NEXT:    ldp x29, x30, [sp], #16 ; 16-byte Folded Reload
+; CHECK-NEXT:    ret
+; CHECK-NEXT:    .loh AdrpAdd Lloh0, Lloh1
+entry:
+  %0 = load i32, ptr @x, align 4
+  ret i32 %0
+}