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[TableGen][CodeGen] Remove DisableEncoding field of Instruction class (#156098)
I believe it became no-op with the removal of the "positionally encoded operands" functionality (b87dc35 is the last commit in the series). There are no changes in the generated files.
1 parent 3e6ec47 commit cc5e896

31 files changed

+238
-450
lines changed

‎llvm/docs/CodeGenerator.rst‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1129,7 +1129,7 @@ for your target. It has the following strengths:
11291129

11301130
def STWU : DForm_1<37, (outs ptr_rc:$ea_res), (ins GPRC:$rS, memri:$dst),
11311131
"stwu $rS, $dst", LdStStoreUpd, []>,
1132-
RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1132+
RegConstraint<"$dst.reg = $ea_res">;
11331133

11341134
def : Pat<(pre_store GPRC:$rS, ptr_rc:$ptrreg, iaddroff:$ptroff),
11351135
(STWU GPRC:$rS, iaddroff:$ptroff, ptr_rc:$ptrreg)>;

‎llvm/include/llvm/Target/Target.td‎

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -735,10 +735,6 @@ class Instruction : InstructionEncoding {
735735
/// discussion of inline assembly constraint strings.
736736
string Constraints = "";
737737

738-
/// DisableEncoding - List of operand names (e.g. "$op1,$op2") that should not
739-
/// be encoded into the output machineinstr.
740-
string DisableEncoding = "";
741-
742738
string PostEncoderMethod = "";
743739

744740
/// Target-specific flags. This becomes the TSFlags field in TargetInstrDesc.

‎llvm/lib/Target/AMDGPU/BUFInstructions.td‎

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -132,7 +132,6 @@ class MTBUF_Real <MTBUF_Pseudo ps, string real_name = ps.Mnemonic> :
132132
let OtherPredicates = ps.OtherPredicates;
133133
let AsmMatchConverter = ps.AsmMatchConverter;
134134
let Constraints = ps.Constraints;
135-
let DisableEncoding = ps.DisableEncoding;
136135
let TSFlags = ps.TSFlags;
137136
let SchedRW = ps.SchedRW;
138137
let mayLoad = ps.mayLoad;
@@ -346,7 +345,6 @@ class MUBUF_Real <MUBUF_Pseudo ps, string real_name = ps.Mnemonic> :
346345
let AsmMatchConverter = ps.AsmMatchConverter;
347346
let OtherPredicates = ps.OtherPredicates;
348347
let Constraints = ps.Constraints;
349-
let DisableEncoding = ps.DisableEncoding;
350348
let TSFlags = ps.TSFlags;
351349
let UseNamedOperandTable = ps.UseNamedOperandTable;
352350
let SchedRW = ps.SchedRW;
@@ -769,7 +767,6 @@ class MUBUF_AtomicRet_Pseudo<string opName, int addrKind,
769767
let sccb_value = 0;
770768
let IsAtomicRet = 1;
771769
let Constraints = "$vdata = $vdata_in";
772-
let DisableEncoding = "$vdata_in";
773770
}
774771

775772
multiclass MUBUF_Pseudo_Atomics_NO_RTN <string opName,
@@ -2414,7 +2411,6 @@ class VBUFFER_Real <bits<8> op, BUF_Pseudo ps, string real_name> :
24142411
let AsmMatchConverter = ps.AsmMatchConverter;
24152412
let OtherPredicates = ps.OtherPredicates;
24162413
let Constraints = ps.Constraints;
2417-
let DisableEncoding = ps.DisableEncoding;
24182414
let TSFlags = ps.TSFlags;
24192415
let UseNamedOperandTable = ps.UseNamedOperandTable;
24202416
let SchedRW = ps.SchedRW;

‎llvm/lib/Target/AMDGPU/DSInstructions.td‎

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -76,7 +76,6 @@ class DS_Real <DS_Pseudo ps, string opName = ps.Mnemonic> :
7676
let isConvergent = ps.isConvergent;
7777

7878
let Constraints = ps.Constraints;
79-
let DisableEncoding = ps.DisableEncoding;
8079

8180
// encoding fields
8281
bits<10> vdst;
@@ -276,7 +275,6 @@ class DS_BVH_STACK<string opName,
276275
data1_rc:$data1, Offset:$offset),
277276
" $vdst, $addr, $data0, $data1$offset"> {
278277
let Constraints = "$addr = $addr_in";
279-
let DisableEncoding = "$addr_in";
280278
let has_gds = 0;
281279
let gdsValue = 0;
282280
// TODO: Use MMOs in the LDS address space instead of hasSideEffects = 1.
@@ -293,7 +291,6 @@ class DS_1A_RET<string opName, RegisterClass rc = VGPR_32, bit HasTiedOutput = 0
293291
(ins VGPR_32:$addr, ofs:$offset, gds:$gds)),
294292
" $vdst, $addr$offset$gds"> {
295293
let Constraints = !if(HasTiedOutput, "$vdst = $vdst_in", "");
296-
let DisableEncoding = !if(HasTiedOutput, "$vdst_in", "");
297294
let has_data0 = 0;
298295
let has_data1 = 0;
299296
}

‎llvm/lib/Target/AMDGPU/EvergreenInstructions.td‎

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -626,7 +626,6 @@ class R600_LDS_1A <bits<6> lds_op, string name, list<dag> pattern> : R600_LDS <
626626

627627
let usesCustomInserter = 1;
628628
let LDS_1A = 1;
629-
let DisableEncoding = "$dst";
630629
}
631630

632631
class R600_LDS_1A1D <bits<6> lds_op, dag outs, string name, list<dag> pattern,
@@ -646,6 +645,7 @@ class R600_LDS_1A1D <bits<6> lds_op, dag outs, string name, list<dag> pattern,
646645
let src2 = 0;
647646
let src2_rel = 0;
648647
let LDS_1A1D = 1;
648+
string DisableEncoding = "";
649649
}
650650

651651
class R600_LDS_1A1D_NORET <bits<6> lds_op, string name, list<dag> pattern> :
@@ -688,7 +688,6 @@ class R600_LDS_1A2D_RET <bits<6> lds_op, string name, list<dag> pattern> :
688688

689689
let BaseOp = name;
690690
let usesCustomInserter = 1;
691-
let DisableEncoding = "$dst";
692691
}
693692

694693
def LDS_ADD : R600_LDS_1A1D_NORET <0x0, "LDS_ADD", [] >;

‎llvm/lib/Target/AMDGPU/FLATInstructions.td‎

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -239,7 +239,6 @@ class FLAT_Load_Pseudo<
239239
let enabled_saddr = EnableSaddr;
240240

241241
let Constraints = !if(HasTiedOutput, "$vdst = $vdst_in", "");
242-
let DisableEncoding = !if(HasTiedOutput, "$vdst_in", "");
243242
}
244243

245244
multiclass FLAT_Flat_Load_Pseudo<string opName, RegisterClass regClass, bit HasTiedInput = 0> {
@@ -335,7 +334,6 @@ class FLAT_Global_Load_AddTid_Pseudo <string opName, RegisterClass regClass,
335334
let enabled_saddr = EnableSaddr;
336335

337336
let Constraints = !if(HasTiedOutput, "$vdst = $vdst_in", "");
338-
let DisableEncoding = !if(HasTiedOutput, "$vdst_in", "");
339337
}
340338

341339
multiclass FLAT_Global_Load_AddTid_Pseudo<string opName, RegisterClass regClass,
@@ -568,7 +566,6 @@ class FLAT_Scratch_Load_Pseudo <string opName, RegisterClass regClass,
568566
let sve = EnableVaddr;
569567

570568
let Constraints = !if(HasTiedOutput, "$vdst = $vdst_in", "");
571-
let DisableEncoding = !if(HasTiedOutput, "$vdst_in", "");
572569
}
573570

574571
class FLAT_Scratch_Store_Pseudo <string opName, RegisterClass vdataClass, bit EnableSaddr = 0,

‎llvm/lib/Target/AMDGPU/R600Instructions.td‎

Lines changed: 3 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -123,7 +123,6 @@ class R600_1OP <bits<11> inst, string opName, list<dag> pattern,
123123
let HasNativeOperands = 1;
124124
let Op1 = 1;
125125
let ALUInst = 1;
126-
let DisableEncoding = "$literal";
127126
let UseNamedOperandTable = 1;
128127

129128
let Inst{31-0} = Word0;
@@ -161,7 +160,6 @@ class R600_2OP <bits<11> inst, string opName, list<dag> pattern,
161160
let HasNativeOperands = 1;
162161
let Op2 = 1;
163162
let ALUInst = 1;
164-
let DisableEncoding = "$literal";
165163
let UseNamedOperandTable = 1;
166164

167165
let Inst{31-0} = Word0;
@@ -201,7 +199,6 @@ class R600_3OP <bits<5> inst, string opName, list<dag> pattern,
201199
R600ALU_Word1_OP3<inst>{
202200

203201
let HasNativeOperands = 1;
204-
let DisableEncoding = "$literal";
205202
let Op3 = 1;
206203
let UseNamedOperandTable = 1;
207204
let ALUInst = 1;
@@ -1783,7 +1780,7 @@ def : DwordAddrPat <i32, R600_Reg32>;
17831780
def getLDSNoRetOp : InstrMapping {
17841781
let FilterClass = "R600_LDS_1A1D";
17851782
let RowFields = ["BaseOp"];
1786-
let ColFields = ["DisableEncoding"];
1787-
let KeyCol = ["$dst"];
1788-
let ValueCols = [[""""]];
1783+
let ColFields = ["usesCustomInserter"];
1784+
let KeyCol = ["1"];
1785+
let ValueCols = [["0"]];
17891786
}

‎llvm/lib/Target/AMDGPU/SIInstructions.td‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -66,7 +66,7 @@ defm V_INTERP_P1_F32_16bank : V_INTERP_P1_F32_m;
6666
// Constraints = "@earlyclobber $vdst", isAsmParserOnly=1
6767

6868
let OtherPredicates = [isNotGFX90APlus] in {
69-
let DisableEncoding = "$src0", Constraints = "$src0 = $vdst" in {
69+
let Constraints = "$src0 = $vdst" in {
7070

7171
defm V_INTERP_P2_F32 : VINTRP_m <
7272
0x00000001,
@@ -77,7 +77,7 @@ defm V_INTERP_P2_F32 : VINTRP_m <
7777
[(set f32:$vdst, (int_amdgcn_interp_p2 f32:$src0, f32:$vsrc,
7878
(i32 timm:$attrchan), (i32 timm:$attr), M0))]>;
7979

80-
} // End DisableEncoding = "$src0", Constraints = "$src0 = $vdst"
80+
} // End Constraints = "$src0 = $vdst"
8181

8282
defm V_INTERP_MOV_F32 : VINTRP_m <
8383
0x00000002,

‎llvm/lib/Target/AMDGPU/SMInstructions.td‎

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -295,7 +295,6 @@ class SM_Pseudo_Atomic<string opName,
295295
let has_soffset = offsets.HasSOffset;
296296

297297
let Constraints = !if(isRet, "$sdst = $sdata", "");
298-
let DisableEncoding = !if(isRet, "$sdata", "");
299298
}
300299

301300
multiclass SM_Pseudo_Atomics<RegisterClass baseClass,
@@ -678,7 +677,6 @@ class SMEM_Atomic_Real_vi <bits<8> op, SM_Atomic_Pseudo ps>
678677
bits<7> sdata;
679678

680679
let Constraints = ps.Constraints;
681-
let DisableEncoding = ps.DisableEncoding;
682680

683681
let cpol{CPolBit.GLC} = ps.glc;
684682
let Inst{12-6} = !if(ps.glc, sdst{6-0}, sdata{6-0});
@@ -1295,7 +1293,6 @@ class SMEM_Atomic_Real_gfx10 <bits<8> op, SM_Atomic_Pseudo ps>
12951293
bits<7> sdata;
12961294

12971295
let Constraints = ps.Constraints;
1298-
let DisableEncoding = ps.DisableEncoding;
12991296

13001297
let cpol{CPolBit.GLC} = ps.glc;
13011298

‎llvm/lib/Target/AMDGPU/SOPInstructions.td‎

Lines changed: 3 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -583,7 +583,6 @@ class SOP2_Real<SOP_Pseudo ps, string name = ps.Mnemonic> :
583583
let mayLoad = ps.mayLoad;
584584
let mayStore = ps.mayStore;
585585
let Constraints = ps.Constraints;
586-
let DisableEncoding = ps.DisableEncoding;
587586
let Uses = ps.Uses;
588587
let Defs = ps.Defs;
589588
let isConvergent = ps.isConvergent;
@@ -934,7 +933,7 @@ let SubtargetPredicate = HasSALUFloatInsts, mayRaiseFPException = 1,
934933
>;
935934
} // End isReMaterializable = 1
936935

937-
let Constraints = "$sdst = $src2", DisableEncoding="$src2",
936+
let Constraints = "$sdst = $src2",
938937
isCommutable = 1, AddedComplexity = 20 in {
939938
def S_FMAC_F32 : SOP2_Pseudo<
940939
"s_fmac_f32", (outs SReg_32:$sdst),
@@ -949,7 +948,7 @@ let SubtargetPredicate = HasSALUFloatInsts, mayRaiseFPException = 1,
949948
"$sdst, $src0, $src1",
950949
[(set f16:$sdst, (UniformTernaryFrag<any_fma> SSrc_f16:$src0, SSrc_f16:$src1, SReg_32:$src2))]
951950
>;
952-
} // End Constraints = "$sdst = $src2", DisableEncoding="$src2",
951+
} // End Constraints = "$sdst = $src2",
953952
// isCommutable = 1, AddedComplexity = 20
954953
} // End SubtargetPredicate = HasSALUFloatInsts, mayRaiseFPException = 1,
955954
// Uses = [MODE], SchedRW = [WriteSFPU]
@@ -994,7 +993,6 @@ class SOPK_Real<SOPK_Pseudo ps, string name = ps.Mnemonic> :
994993
// copy relevant pseudo op flags
995994
let SubtargetPredicate = ps.SubtargetPredicate;
996995
let AsmMatchConverter = ps.AsmMatchConverter;
997-
let DisableEncoding = ps.DisableEncoding;
998996
let Constraints = ps.Constraints;
999997
let SchedRW = ps.SchedRW;
1000998
let mayLoad = ps.mayLoad;
@@ -1116,8 +1114,7 @@ def S_CMPK_LT_U32 : SOPK_SCC <"s_cmpk_lt_u32", "s_cmp_lt_u32", 0>;
11161114
def S_CMPK_LE_U32 : SOPK_SCC <"s_cmpk_le_u32", "s_cmp_le_u32", 0>;
11171115
} // End isCompare = 1
11181116

1119-
let isCommutable = 1, DisableEncoding = "$src0",
1120-
Constraints = "$sdst = $src0" in {
1117+
let isCommutable = 1, Constraints = "$sdst = $src0" in {
11211118
let Defs = [SCC] in
11221119
def S_ADDK_I32 : SOPK_32TIE <"s_addk_i32">;
11231120
def S_MULK_I32 : SOPK_32TIE <"s_mulk_i32">;

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