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[CIR] Implement codegen for inline assembly without input and output operands (#153546)
- Part of #153267 https://github.com/llvm/clangir/blob/main/clang/lib/CIR/CodeGen/CIRAsm.cpp
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‎clang/include/clang/CIR/MissingFeatures.h

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@@ -175,7 +175,12 @@ struct MissingFeatures {
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static bool aggValueSlotVolatile() { return false; }
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static bool alignCXXRecordDecl() { return false; }
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static bool armComputeVolatileBitfields() { return false; }
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static bool asmGoto() { return false; }
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static bool asmInputOperands() { return false; }
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static bool asmLabelAttr() { return false; }
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static bool asmMemoryEffects() { return false; }
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static bool asmOutputOperands() { return false; }
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static bool asmUnwindClobber() { return false; }
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static bool assignMemcpyizer() { return false; }
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static bool astVarDeclInterface() { return false; }
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static bool attributeBuiltin() { return false; }

‎clang/lib/CIR/CodeGen/CIRGenAsm.cpp

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//===--- CIRGenAsm.cpp - Inline Assembly Support for CIR CodeGen ---------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains code to emit inline assembly.
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//
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//===----------------------------------------------------------------------===//
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#include "CIRGenFunction.h"
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#include "clang/CIR/MissingFeatures.h"
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using namespace clang;
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using namespace clang::CIRGen;
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using namespace cir;
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static AsmFlavor inferFlavor(const CIRGenModule &cgm, const AsmStmt &s) {
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AsmFlavor gnuAsmFlavor =
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cgm.getCodeGenOpts().getInlineAsmDialect() == CodeGenOptions::IAD_ATT
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? AsmFlavor::x86_att
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: AsmFlavor::x86_intel;
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return isa<MSAsmStmt>(&s) ? AsmFlavor::x86_intel : gnuAsmFlavor;
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}
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static void collectClobbers(const CIRGenFunction &cgf, const AsmStmt &s,
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std::string &constraints, bool &hasUnwindClobber,
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bool &readOnly, bool readNone) {
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hasUnwindClobber = false;
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const CIRGenModule &cgm = cgf.getCIRGenModule();
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// Clobbers
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for (unsigned i = 0, e = s.getNumClobbers(); i != e; i++) {
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std::string clobber = s.getClobber(i);
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if (clobber == "memory") {
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readOnly = readNone = false;
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} else if (clobber == "unwind") {
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hasUnwindClobber = true;
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continue;
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} else if (clobber != "cc") {
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clobber = cgf.getTarget().getNormalizedGCCRegisterName(clobber);
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if (cgm.getCodeGenOpts().StackClashProtector &&
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cgf.getTarget().isSPRegName(clobber))
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cgm.getDiags().Report(s.getAsmLoc(),
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diag::warn_stack_clash_protection_inline_asm);
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}
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if (isa<MSAsmStmt>(&s)) {
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if (clobber == "eax" || clobber == "edx") {
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if (constraints.find("=&A") != std::string::npos)
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continue;
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std::string::size_type position1 =
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constraints.find("={" + clobber + "}");
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if (position1 != std::string::npos) {
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constraints.insert(position1 + 1, "&");
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continue;
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}
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std::string::size_type position2 = constraints.find("=A");
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if (position2 != std::string::npos) {
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constraints.insert(position2 + 1, "&");
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continue;
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}
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}
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}
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if (!constraints.empty())
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constraints += ',';
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constraints += "~{";
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constraints += clobber;
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constraints += '}';
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}
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// Add machine specific clobbers
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std::string_view machineClobbers = cgf.getTarget().getClobbers();
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if (!machineClobbers.empty()) {
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if (!constraints.empty())
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constraints += ',';
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constraints += machineClobbers;
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}
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}
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mlir::LogicalResult CIRGenFunction::emitAsmStmt(const AsmStmt &s) {
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// Assemble the final asm string.
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std::string asmString = s.generateAsmString(getContext());
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bool isGCCAsmGoto = false;
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std::string constraints;
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std::vector<mlir::Value> outArgs;
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std::vector<mlir::Value> inArgs;
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std::vector<mlir::Value> inOutArgs;
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// An inline asm can be marked readonly if it meets the following conditions:
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// - it doesn't have any sideeffects
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// - it doesn't clobber memory
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// - it doesn't return a value by-reference
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// It can be marked readnone if it doesn't have any input memory constraints
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// in addition to meeting the conditions listed above.
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bool readOnly = true, readNone = true;
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if (s.getNumInputs() != 0 || s.getNumOutputs() != 0) {
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assert(!cir::MissingFeatures::asmInputOperands());
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assert(!cir::MissingFeatures::asmOutputOperands());
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cgm.errorNYI(s.getAsmLoc(), "asm with operands");
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}
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bool hasUnwindClobber = false;
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collectClobbers(*this, s, constraints, hasUnwindClobber, readOnly, readNone);
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std::array<mlir::ValueRange, 3> operands = {outArgs, inArgs, inOutArgs};
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mlir::Type resultType;
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bool hasSideEffect = s.isVolatile() || s.getNumOutputs() == 0;
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cir::InlineAsmOp ia = builder.create<cir::InlineAsmOp>(
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getLoc(s.getAsmLoc()), resultType, operands, asmString, constraints,
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hasSideEffect, inferFlavor(cgm, s), mlir::ArrayAttr());
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if (isGCCAsmGoto) {
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assert(!cir::MissingFeatures::asmGoto());
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} else if (hasUnwindClobber) {
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assert(!cir::MissingFeatures::asmUnwindClobber());
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} else {
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assert(!cir::MissingFeatures::asmMemoryEffects());
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}
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llvm::SmallVector<mlir::Attribute> operandAttrs;
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ia.setOperandAttrsAttr(builder.getArrayAttr(operandAttrs));
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return mlir::success();
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}

‎clang/lib/CIR/CodeGen/CIRGenFunction.h

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@@ -954,6 +954,8 @@ class CIRGenFunction : public CIRGenTypeCache {
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Address emitArrayToPointerDecay(const Expr *array);
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mlir::LogicalResult emitAsmStmt(const clang::AsmStmt &s);
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RValue emitAtomicExpr(AtomicExpr *e);
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void emitAtomicInit(Expr *init, LValue dest);
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‎clang/lib/CIR/CodeGen/CIRGenModule.h

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@@ -102,6 +102,7 @@ class CIRGenModule : public CIRGenTypeCache {
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clang::ASTContext &getASTContext() const { return astContext; }
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const clang::TargetInfo &getTarget() const { return target; }
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const clang::CodeGenOptions &getCodeGenOpts() const { return codeGenOpts; }
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clang::DiagnosticsEngine &getDiags() const { return diags; }
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CIRGenTypes &getTypes() { return genTypes; }
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const clang::LangOptions &getLangOpts() const { return langOpts; }
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‎clang/lib/CIR/CodeGen/CIRGenStmt.cpp

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@@ -132,6 +132,9 @@ mlir::LogicalResult CIRGenFunction::emitStmt(const Stmt *s,
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return emitOpenACCCacheConstruct(cast<OpenACCCacheConstruct>(*s));
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case Stmt::OpenACCAtomicConstructClass:
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return emitOpenACCAtomicConstruct(cast<OpenACCAtomicConstruct>(*s));
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case Stmt::GCCAsmStmtClass:
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case Stmt::MSAsmStmtClass:
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return emitAsmStmt(cast<AsmStmt>(*s));
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case Stmt::OMPScopeDirectiveClass:
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case Stmt::OMPErrorDirectiveClass:
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case Stmt::LabelStmtClass:
@@ -145,8 +148,6 @@ mlir::LogicalResult CIRGenFunction::emitStmt(const Stmt *s,
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case Stmt::CoreturnStmtClass:
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case Stmt::CXXTryStmtClass:
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case Stmt::IndirectGotoStmtClass:
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case Stmt::GCCAsmStmtClass:
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case Stmt::MSAsmStmtClass:
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case Stmt::OMPParallelDirectiveClass:
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case Stmt::OMPTaskwaitDirectiveClass:
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case Stmt::OMPTaskyieldDirectiveClass:

‎clang/lib/CIR/CodeGen/CMakeLists.txt

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@@ -8,6 +8,7 @@ get_property(dialect_libs GLOBAL PROPERTY MLIR_DIALECT_LIBS)
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add_clang_library(clangCIR
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CIRGenerator.cpp
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CIRGenAsm.cpp
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CIRGenAtomic.cpp
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CIRGenBuilder.cpp
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CIRGenCall.cpp

‎clang/test/CIR/CodeGen/inline-asm.c

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// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -Wno-unused-value -fclangir -emit-cir %s -o %t.cir
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// RUN: FileCheck --input-file=%t.cir %s -check-prefix=CIR
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// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -fclangir -emit-llvm %s -o %t-cir.ll
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// RUN: FileCheck --input-file=%t-cir.ll %s --check-prefix=LLVM
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void f1() {
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// CIR: cir.asm(x86_att,
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// CIR: out = [],
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// CIR: in = [],
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// CIR: in_out = [],
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// CIR: {"" "~{dirflag},~{fpsr},~{flags}"}) side_effects
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// LLVM: call void asm sideeffect "", "~{dirflag},~{fpsr},~{flags}"()
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__asm__ volatile("" : : : );
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}
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void f2() {
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// CIR: cir.asm(x86_att,
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// CIR: out = [],
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// CIR: in = [],
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// CIR: in_out = [],
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// CIR: {"nop" "~{dirflag},~{fpsr},~{flags}"}) side_effects
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// LLVM: call void asm sideeffect "nop", "~{dirflag},~{fpsr},~{flags}"()
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__asm__ volatile("nop" : : : );
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}

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