Remove "FeatureStdExtZicsr" from RISCVProcessors.td

liliumShade · liliumShade · commit cca4fb25f86c · 2025-04-18T10:48:24.000+08:00
diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -561,8 +561,7 @@ def XIANGSHAN_NANHU : RISCVProcessorModel<"xiangshan-nanhu",
 def XIANGSHAN_KUNMINGHU : RISCVProcessorModel<"xiangshan-kunminghu",
                                               NoSchedModel,
                                               !listconcat(RVA23S64Features,
-                                              [FeatureStdExtZicsr,
-                                               FeatureStdExtZacas,
+                                              [FeatureStdExtZacas,
                                                FeatureStdExtZbc,
                                                FeatureStdExtZfh,
                                                FeatureStdExtZkn,
