[AMDGPU] Enhance verification of amdgcn.cs.chain intrinsic

Make sure that this intrinsic is being followed by unreachable.

This LLVM defect was identified via the AMD Fuzzing project.

Author: ro-i

llvm/lib/IR/Verifier.cpp

@@ -6367,6 +6367,8 @@ void Verifier::visitIntrinsicCall(Intrinsic::ID ID, CallBase &Call) {
           "SGPR arguments must have the `inreg` attribute", &Call);
     Check(!Call.paramHasAttr(3, Attribute::InReg),
           "VGPR arguments must not have the `inreg` attribute", &Call);
+    Check(dyn_cast_or_null<UnreachableInst>(Call.getNextNode()),
+          "amdgcn_cs_chain must precede unreachable", &Call);
     break;
   }
   case Intrinsic::amdgcn_set_inactive_chain_arg: {

llvm/test/Verifier/AMDGPU/intrinsic-amdgpu-cs-chain.ll

@@ -32,6 +32,13 @@ define amdgpu_cs_chain void @bad_exec(ptr %fn, i32 %exec, <4 x i32> inreg %sgpr,
   unreachable
 }
 
+define amdgpu_cs_chain void @not_unreachable(ptr %fn, i32 %exec, <4 x i32> inreg %sgpr, { ptr, <3 x i32> } %vgpr) {
+  ; CHECK: amdgcn_cs_chain must precede unreachable
+  ; CHECK-NEXT: @llvm.amdgcn.cs.chain
+  call void(ptr, i32, <4 x i32>, { ptr, <3 x i32> }, i32, ...) @llvm.amdgcn.cs.chain(ptr %fn, i32 %exec, <4 x i32> inreg %sgpr, { ptr, <3 x i32> } %vgpr, i32 0)
+  ret void
+}
+
 define void @bad_caller_default_cc(ptr %fn, i32 %exec, <4 x i32> inreg %sgpr, { ptr, <3 x i32> } %vgpr) {
   ; CHECK: Intrinsic can only be used from functions with the amdgpu_cs_chain or amdgpu_cs_chain_preserve calling conventions
   ; CHECK-NEXT: @llvm.amdgcn.set.inactive.chain.arg
@@ -117,4 +124,4 @@ define amdgpu_cs_chain void @set_inactive_chain_arg_inreg(ptr addrspace(1) %out,
   %tmp = call i32 @llvm.amdgcn.set.inactive.chain.arg(i32 %active, i32 inreg %inactive) #0
   store i32 %tmp, ptr addrspace(1) %out
   ret void
-}
+}