Use iterator wrappers for superclasses

Author: resistor

llvm/include/llvm/CodeGen/TargetRegisterInfo.h

@@ -42,11 +42,27 @@ class VirtRegMap;
 class LiveIntervals;
 class LiveInterval;
 
+/// TargetSuperClassIterator enumerates all super-registers of RegClass.
+class TargetSuperClassIterator
+    : public iterator_adaptor_base<TargetSuperClassIterator, const unsigned *> {
+public:
+  /// Constructs an end iterator.
+  TargetSuperClassIterator() = default;
+
+  TargetSuperClassIterator(const unsigned *V) { I = V; }
+
+  const unsigned &operator*() const { return *I; }
+
+  using iterator_adaptor_base::operator++;
+
+  /// Returns true if this iterator is not yet at the end.
+  bool isValid() const { return I && *I != ~0U; }
+};
+
 class TargetRegisterClass {
 public:
   using iterator = const MCPhysReg *;
   using const_iterator = const MCPhysReg *;
-  using sc_iterator = const unsigned *;
 
   // Instance variables filled by tablegen, do not use!
   const MCRegisterClass *MC;
@@ -67,7 +83,7 @@ class TargetRegisterClass {
   /// Whether a combination of subregisters can cover every register in the
   /// class. See also the CoveredBySubRegs description in Target.td.
   const bool CoveredBySubRegs;
-  const sc_iterator SuperClasses;
+  const unsigned *SuperClasses;
   ArrayRef<MCPhysReg> (*OrderFunc)(const MachineFunction&);
 
   /// Return the register class ID number.
@@ -178,8 +194,8 @@ class TargetRegisterClass {
   /// Returns a NULL-terminated list of super-classes.  The
   /// classes are ordered by ID which is also a topological ordering from large
   /// to small classes.  The list does NOT include the current class.
-  sc_iterator getSuperClasses() const {
-    return SuperClasses;
+  iterator_range<TargetSuperClassIterator> superclasses() const {
+    return make_range({SuperClasses}, TargetSuperClassIterator());
   }
 
   /// Return true if this TargetRegisterClass is a subset

llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp

@@ -263,7 +263,7 @@ const TargetRegisterClass *
 ARMBaseRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC,
                                                const MachineFunction &MF) const {
   unsigned SuperID = RC->getID();
-  TargetRegisterClass::sc_iterator I = RC->getSuperClasses();
+  auto I = RC->superclasses().begin();
   do {
     switch (SuperID) {
     case ARM::GPRRegClassID:

llvm/lib/Target/Hexagon/HexagonRegisterInfo.cpp

@@ -431,7 +431,7 @@ unsigned HexagonRegisterInfo::getHexagonSubRegIndex(
       return WSub[GenIdx];
   }
 
-  unsigned SuperID = *RC.getSuperClasses();
+  unsigned SuperID = *RC.superclasses().begin();
   if (SuperID != ~0U)
     return getHexagonSubRegIndex(*getRegClass(SuperID), GenIdx);
 

llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp

@@ -692,22 +692,23 @@ PPCRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC,
         InflateGPRC++;
     }
 
-    for (const unsigned *I = RC->getSuperClasses(); *I != ~0U; ++I) {
-      if (getRegSizeInBits(*getRegClass(*I)) != getRegSizeInBits(*RC))
+    for (unsigned SuperID : RC->superclasses()) {
+      if (getRegSizeInBits(*getRegClass(SuperID)) != getRegSizeInBits(*RC))
         continue;
 
-      switch (*I) {
+      switch (SuperID) {
       case PPC::VSSRCRegClassID:
-        return Subtarget.hasP8Vector() ? getRegClass(*I) : DefaultSuperclass;
+        return Subtarget.hasP8Vector() ? getRegClass(SuperID)
+                                       : DefaultSuperclass;
       case PPC::VSFRCRegClassID:
       case PPC::VSRCRegClassID:
-        return getRegClass(*I);
+        return getRegClass(SuperID);
       case PPC::VSRpRCRegClassID:
-        return Subtarget.pairedVectorMemops() ? getRegClass(*I)
+        return Subtarget.pairedVectorMemops() ? getRegClass(SuperID)
                                               : DefaultSuperclass;
       case PPC::ACCRCRegClassID:
       case PPC::UACCRCRegClassID:
-        return Subtarget.hasMMA() ? getRegClass(*I) : DefaultSuperclass;
+        return Subtarget.hasMMA() ? getRegClass(SuperID) : DefaultSuperclass;
       }
     }
   }

llvm/lib/Target/X86/X86RegisterInfo.cpp

@@ -123,7 +123,7 @@ X86RegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC,
   const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
 
   const TargetRegisterClass *Super = RC;
-  TargetRegisterClass::sc_iterator I = RC->getSuperClasses();
+  auto I = RC->superclasses().begin();
   do {
     switch (Super->getID()) {
     case X86::FR32RegClassID:
@@ -172,7 +172,7 @@ X86RegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC,
       if (getRegSizeInBits(*Super) == getRegSizeInBits(*RC))
         return Super;
     }
-    Super = (*I != ~0U) ? getRegClass(*I) : nullptr;
+    Super = I.isValid() ? getRegClass(*I) : nullptr;
     ++I;
   } while (Super);
   return RC;