[SelectionDAG] Fix incorrect fold condition in foldSetCCWithFunnelShift.

Author: Ruhung

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

@@ -4462,11 +4462,14 @@ static SDValue foldSetCCWithFunnelShift(EVT VT, SDValue N0, SDValue N1,
 
   unsigned BitWidth = N0.getScalarValueSizeInBits();
   auto *ShAmtC = isConstOrConstSplat(N0.getOperand(2));
-  if (!ShAmtC || ShAmtC->getAPIntValue().uge(BitWidth))
+  if (!ShAmtC)
+    return SDValue();
+
+  uint64_t ShAmt = ShAmtC->getAPIntValue().urem(BitWidth);
+  if (ShAmt == 0)
     return SDValue();
 
   // Canonicalize fshr as fshl to reduce pattern-matching.
-  unsigned ShAmt = ShAmtC->getZExtValue();
   if (N0.getOpcode() == ISD::FSHR)
     ShAmt = BitWidth - ShAmt;
 

llvm/test/CodeGen/AArch64/setcc-fsh.ll

@@ -252,7 +252,8 @@ define i1 @fshl_or_ne_2(i32 %x, i32 %y) {
 define i1 @fshr_0_or_eq_0(i16 %x, i16 %y) {
 ; CHECK-LABEL: fshr_0_or_eq_0:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w0, wzr
+; CHECK-NEXT:    tst w0, #0xffff
+; CHECK-NEXT:    cset w0, eq
 ; CHECK-NEXT:    ret
   %or = or i16 %x, %y
   %f = call i16 @llvm.fshr.i16(i16 %or, i16 %x, i16 0)
@@ -261,7 +262,7 @@ define i1 @fshr_0_or_eq_0(i16 %x, i16 %y) {
 }
 
 define i1 @fshr_32_or_eq_0(i16 %x, i16 %y) {
-; CHECK-LABEL: fshr_16_or_eq_0:
+; CHECK-LABEL: fshr_32_or_eq_0:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    tst w0, #0xffff
 ; CHECK-NEXT:    cset w0, eq