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[RISCV] Assign different scheduling classes for VMADC/VMSBC
Split the scheduling classes of VMADC/VMSBC away from that of VADC/VSBC. Because the former are technically mask-producing instructions rather than normal vector arithmetics, which might have different performance characteristics on some processors. This is effectively NFC.
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6 files changed

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-16
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‎llvm/lib/Target/RISCV/RISCVInstrInfoV.td‎

Lines changed: 18 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -630,31 +630,43 @@ multiclass VMRG_IV_V_X_I<string opcodestr, bits<6> funct6> {
630630
}
631631

632632
multiclass VALUm_IV_V_X<string opcodestr, bits<6> funct6> {
633+
// if LSB of funct6 is 1, it's a mask-producing instruction that
634+
// uses a different scheduling class.
635+
defvar WritePrefix = !if(funct6{0}, "WriteVICALUM", "WriteVICALU");
633636
def VM : VALUmVV<funct6, OPIVV, opcodestr # ".vvm">,
634-
SchedBinaryMC<"WriteVICALUV", "ReadVICALUV", "ReadVICALUV">;
637+
SchedBinaryMC<WritePrefix#"V", "ReadVICALUV", "ReadVICALUV">;
635638
def XM : VALUmVX<funct6, OPIVX, opcodestr # ".vxm">,
636-
SchedBinaryMC<"WriteVICALUX", "ReadVICALUV", "ReadVICALUX">;
639+
SchedBinaryMC<WritePrefix#"X", "ReadVICALUV", "ReadVICALUX">;
637640
}
638641

639642
multiclass VALUm_IV_V_X_I<string opcodestr, bits<6> funct6>
640643
: VALUm_IV_V_X<opcodestr, funct6> {
644+
// if LSB of funct6 is 1, it's a mask-producing instruction that
645+
// uses a different scheduling class.
646+
defvar WriteSched = !if(funct6{0}, "WriteVICALUMI", "WriteVICALUI");
641647
def IM : VALUmVI<funct6, opcodestr # ".vim">,
642-
SchedUnaryMC<"WriteVICALUI", "ReadVICALUV">;
648+
SchedUnaryMC<WriteSched, "ReadVICALUV">;
643649
}
644650

645651
multiclass VALUNoVm_IV_V_X<string opcodestr, bits<6> funct6> {
652+
// if LSB of funct6 is 1, it's a mask-producing instruction that
653+
// uses a different scheduling class.
654+
defvar WritePrefix = !if(funct6{0}, "WriteVICALUM", "WriteVICALU");
646655
def V : VALUVVNoVm<funct6, OPIVV, opcodestr # ".vv">,
647-
SchedBinaryMC<"WriteVICALUV", "ReadVICALUV", "ReadVICALUV",
656+
SchedBinaryMC<WritePrefix#"V", "ReadVICALUV", "ReadVICALUV",
648657
forceMasked=0>;
649658
def X : VALUVXNoVm<funct6, OPIVX, opcodestr # ".vx">,
650-
SchedBinaryMC<"WriteVICALUX", "ReadVICALUV", "ReadVICALUX",
659+
SchedBinaryMC<WritePrefix#"X", "ReadVICALUV", "ReadVICALUX",
651660
forceMasked=0>;
652661
}
653662

654663
multiclass VALUNoVm_IV_V_X_I<string opcodestr, bits<6> funct6>
655664
: VALUNoVm_IV_V_X<opcodestr, funct6> {
665+
// if LSB of funct6 is 1, it's a mask-producing instruction that
666+
// uses a different scheduling class.
667+
defvar WriteSched = !if(funct6{0}, "WriteVICALUMI", "WriteVICALUI");
656668
def I : VALUVINoVm<funct6, opcodestr # ".vi">,
657-
SchedUnaryMC<"WriteVICALUI", "ReadVICALUV", forceMasked=0>;
669+
SchedUnaryMC<WriteSched, "ReadVICALUV", forceMasked=0>;
658670
}
659671

660672
multiclass VALU_FV_F<string opcodestr, bits<6> funct6> {

‎llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td‎

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -3072,13 +3072,13 @@ multiclass VPseudoVCALUM_VM_XM_IM {
30723072
defvar mx = m.MX;
30733073
defm "" : VPseudoBinaryV_VM<m, CarryOut=1, CarryIn=1, Constraint=constraint,
30743074
Commutable=1, TargetConstraintType=2>,
3075-
SchedBinary<"WriteVICALUV", "ReadVICALUV", "ReadVICALUV", mx, forceMasked=1,
3075+
SchedBinary<"WriteVICALUMV", "ReadVICALUV", "ReadVICALUV", mx, forceMasked=1,
30763076
forcePassthruRead=true>;
30773077
defm "" : VPseudoBinaryV_XM<m, CarryOut=1, CarryIn=1, Constraint=constraint, TargetConstraintType=2>,
3078-
SchedBinary<"WriteVICALUX", "ReadVICALUV", "ReadVICALUX", mx, forceMasked=1,
3078+
SchedBinary<"WriteVICALUMX", "ReadVICALUV", "ReadVICALUX", mx, forceMasked=1,
30793079
forcePassthruRead=true>;
30803080
defm "" : VPseudoBinaryV_IM<m, CarryOut=1, CarryIn=1, Constraint=constraint, TargetConstraintType=2>,
3081-
SchedUnary<"WriteVICALUI", "ReadVICALUV", mx, forceMasked=1,
3081+
SchedUnary<"WriteVICALUMI", "ReadVICALUV", mx, forceMasked=1,
30823082
forcePassthruRead=true>;
30833083
}
30843084
}
@@ -3089,11 +3089,11 @@ multiclass VPseudoVCALUM_VM_XM {
30893089
defvar mx = m.MX;
30903090
defm "" : VPseudoBinaryV_VM<m, CarryOut=1, CarryIn=1, Constraint=constraint,
30913091
TargetConstraintType=2>,
3092-
SchedBinary<"WriteVICALUV", "ReadVICALUV", "ReadVICALUV", mx, forceMasked=1,
3092+
SchedBinary<"WriteVICALUMV", "ReadVICALUV", "ReadVICALUV", mx, forceMasked=1,
30933093
forcePassthruRead=true>;
30943094
defm "" : VPseudoBinaryV_XM<m, CarryOut=1, CarryIn=1, Constraint=constraint,
30953095
TargetConstraintType=2>,
3096-
SchedBinary<"WriteVICALUX", "ReadVICALUV", "ReadVICALUX", mx, forceMasked=1,
3096+
SchedBinary<"WriteVICALUMX", "ReadVICALUV", "ReadVICALUX", mx, forceMasked=1,
30973097
forcePassthruRead=true>;
30983098
}
30993099
}
@@ -3104,13 +3104,13 @@ multiclass VPseudoVCALUM_V_X_I {
31043104
defvar mx = m.MX;
31053105
defm "" : VPseudoBinaryV_VM<m, CarryOut=1, CarryIn=0, Constraint=constraint,
31063106
Commutable=1, TargetConstraintType=2>,
3107-
SchedBinary<"WriteVICALUV", "ReadVICALUV", "ReadVICALUV", mx,
3107+
SchedBinary<"WriteVICALUMV", "ReadVICALUV", "ReadVICALUV", mx,
31083108
forcePassthruRead=true>;
31093109
defm "" : VPseudoBinaryV_XM<m, CarryOut=1, CarryIn=0, Constraint=constraint, TargetConstraintType=2>,
3110-
SchedBinary<"WriteVICALUX", "ReadVICALUV", "ReadVICALUX", mx,
3110+
SchedBinary<"WriteVICALUMX", "ReadVICALUV", "ReadVICALUX", mx,
31113111
forcePassthruRead=true>;
31123112
defm "" : VPseudoBinaryV_IM<m, CarryOut=1, CarryIn=0, Constraint=constraint>,
3113-
SchedUnary<"WriteVICALUI", "ReadVICALUV", mx,
3113+
SchedUnary<"WriteVICALUMI", "ReadVICALUV", mx,
31143114
forcePassthruRead=true>;
31153115
}
31163116
}
@@ -3120,10 +3120,10 @@ multiclass VPseudoVCALUM_V_X {
31203120
foreach m = MxList in {
31213121
defvar mx = m.MX;
31223122
defm "" : VPseudoBinaryV_VM<m, CarryOut=1, CarryIn=0, Constraint=constraint, TargetConstraintType=2>,
3123-
SchedBinary<"WriteVICALUV", "ReadVICALUV", "ReadVICALUV", mx,
3123+
SchedBinary<"WriteVICALUMV", "ReadVICALUV", "ReadVICALUV", mx,
31243124
forcePassthruRead=true>;
31253125
defm "" : VPseudoBinaryV_XM<m, CarryOut=1, CarryIn=0, Constraint=constraint, TargetConstraintType=2>,
3126-
SchedBinary<"WriteVICALUX", "ReadVICALUV", "ReadVICALUX", mx,
3126+
SchedBinary<"WriteVICALUMX", "ReadVICALUV", "ReadVICALUX", mx,
31273127
forcePassthruRead=true>;
31283128
}
31293129
}

‎llvm/lib/Target/RISCV/RISCVSchedSiFive7.td‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -631,6 +631,9 @@ foreach mx = SchedMxList in {
631631
defm "" : LMULWriteResMX<"WriteVICALUV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
632632
defm "" : LMULWriteResMX<"WriteVICALUX", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
633633
defm "" : LMULWriteResMX<"WriteVICALUI", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
634+
defm "" : LMULWriteResMX<"WriteVICALUMV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
635+
defm "" : LMULWriteResMX<"WriteVICALUMX", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
636+
defm "" : LMULWriteResMX<"WriteVICALUMI", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
634637
defm "" : LMULWriteResMX<"WriteVShiftV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
635638
defm "" : LMULWriteResMX<"WriteVShiftX", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
636639
defm "" : LMULWriteResMX<"WriteVShiftI", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;

‎llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -467,6 +467,9 @@ foreach mx = SchedMxList in {
467467
defm "" : LMULWriteResMX<"WriteVICALUV", [SiFiveP400VEXQ0], mx, IsWorstCase>;
468468
defm "" : LMULWriteResMX<"WriteVICALUX", [SiFiveP400VEXQ0], mx, IsWorstCase>;
469469
defm "" : LMULWriteResMX<"WriteVICALUI", [SiFiveP400VEXQ0], mx, IsWorstCase>;
470+
defm "" : LMULWriteResMX<"WriteVICALUMV", [SiFiveP400VEXQ0], mx, IsWorstCase>;
471+
defm "" : LMULWriteResMX<"WriteVICALUMX", [SiFiveP400VEXQ0], mx, IsWorstCase>;
472+
defm "" : LMULWriteResMX<"WriteVICALUMI", [SiFiveP400VEXQ0], mx, IsWorstCase>;
470473
defm "" : LMULWriteResMX<"WriteVICmpV", [SiFiveP400VEXQ0], mx, IsWorstCase>;
471474
defm "" : LMULWriteResMX<"WriteVICmpX", [SiFiveP400VEXQ0], mx, IsWorstCase>;
472475
defm "" : LMULWriteResMX<"WriteVICmpI", [SiFiveP400VEXQ0], mx, IsWorstCase>;

‎llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -403,6 +403,9 @@ foreach mx = SchedMxList in {
403403
defm "" : LMULWriteResMX<"WriteVICALUV", [SiFiveP600VectorArith], mx, IsWorstCase>;
404404
defm "" : LMULWriteResMX<"WriteVICALUX", [SiFiveP600VectorArith], mx, IsWorstCase>;
405405
defm "" : LMULWriteResMX<"WriteVICALUI", [SiFiveP600VectorArith], mx, IsWorstCase>;
406+
defm "" : LMULWriteResMX<"WriteVICALUMV", [SiFiveP600VectorArith], mx, IsWorstCase>;
407+
defm "" : LMULWriteResMX<"WriteVICALUMX", [SiFiveP600VectorArith], mx, IsWorstCase>;
408+
defm "" : LMULWriteResMX<"WriteVICALUMI", [SiFiveP600VectorArith], mx, IsWorstCase>;
406409
defm "" : LMULWriteResMX<"WriteVICmpV", [SiFiveP600VectorArith], mx, IsWorstCase>;
407410
defm "" : LMULWriteResMX<"WriteVICmpX", [SiFiveP600VectorArith], mx, IsWorstCase>;
408411
defm "" : LMULWriteResMX<"WriteVICmpI", [SiFiveP600VectorArith], mx, IsWorstCase>;

‎llvm/lib/Target/RISCV/RISCVScheduleV.td‎

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -364,6 +364,9 @@ defm "" : LMULSchedWrites<"WriteVExtV">;
364364
defm "" : LMULSchedWrites<"WriteVICALUV">;
365365
defm "" : LMULSchedWrites<"WriteVICALUX">;
366366
defm "" : LMULSchedWrites<"WriteVICALUI">;
367+
defm "" : LMULSchedWrites<"WriteVICALUMV">;
368+
defm "" : LMULSchedWrites<"WriteVICALUMX">;
369+
defm "" : LMULSchedWrites<"WriteVICALUMI">;
367370
// 11.6. Vector Single-Width Bit Shift Instructions
368371
defm "" : LMULSchedWrites<"WriteVShiftV">;
369372
defm "" : LMULSchedWrites<"WriteVShiftX">;
@@ -856,6 +859,9 @@ defm "" : LMULWriteRes<"WriteVExtV", []>;
856859
defm "" : LMULWriteRes<"WriteVICALUV", []>;
857860
defm "" : LMULWriteRes<"WriteVICALUX", []>;
858861
defm "" : LMULWriteRes<"WriteVICALUI", []>;
862+
defm "" : LMULWriteRes<"WriteVICALUMV", []>;
863+
defm "" : LMULWriteRes<"WriteVICALUMX", []>;
864+
defm "" : LMULWriteRes<"WriteVICALUMI", []>;
859865
defm "" : LMULWriteRes<"WriteVShiftV", []>;
860866
defm "" : LMULWriteRes<"WriteVShiftX", []>;
861867
defm "" : LMULWriteRes<"WriteVShiftI", []>;

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