Do the same for XCore, RISC_V, and M68k

Author: AZero13

llvm/lib/Target/M68k/M68kInstrInfo.h

@@ -56,42 +56,9 @@ enum CondCode {
 // mb tag based
 
 static inline M68k::CondCode GetOppositeBranchCondition(M68k::CondCode CC) {
-  switch (CC) {
-  default:
-    llvm_unreachable("Illegal condition code!");
-  case M68k::COND_T:
-    return M68k::COND_F;
-  case M68k::COND_F:
-    return M68k::COND_T;
-  case M68k::COND_HI:
-    return M68k::COND_LS;
-  case M68k::COND_LS:
-    return M68k::COND_HI;
-  case M68k::COND_CC:
-    return M68k::COND_CS;
-  case M68k::COND_CS:
-    return M68k::COND_CC;
-  case M68k::COND_NE:
-    return M68k::COND_EQ;
-  case M68k::COND_EQ:
-    return M68k::COND_NE;
-  case M68k::COND_VC:
-    return M68k::COND_VS;
-  case M68k::COND_VS:
-    return M68k::COND_VC;
-  case M68k::COND_PL:
-    return M68k::COND_MI;
-  case M68k::COND_MI:
-    return M68k::COND_PL;
-  case M68k::COND_GE:
-    return M68k::COND_LT;
-  case M68k::COND_LT:
-    return M68k::COND_GE;
-  case M68k::COND_GT:
-    return M68k::COND_LE;
-  case M68k::COND_LE:
-    return M68k::COND_GT;
-  }
+  // To reverse a condition it's necessary to only invert the low bit:
+  assert(CC != COND_INVALID && "COND_INVALID has no inverse!");
+  return static_cast<CondCode>(static_cast<unsigned>(CC) ^ 0x1);
 }
 
 static inline unsigned GetCondBranchFromCond(M68k::CondCode CC) {

llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

@@ -1128,25 +1128,6 @@ unsigned RISCVCC::getBrCond(RISCVCC::CondCode CC, unsigned SelectOpc) {
   }
 }
 
-RISCVCC::CondCode RISCVCC::getOppositeBranchCondition(RISCVCC::CondCode CC) {
-  switch (CC) {
-  default:
-    llvm_unreachable("Unrecognized conditional branch");
-  case RISCVCC::COND_EQ:
-    return RISCVCC::COND_NE;
-  case RISCVCC::COND_NE:
-    return RISCVCC::COND_EQ;
-  case RISCVCC::COND_LT:
-    return RISCVCC::COND_GE;
-  case RISCVCC::COND_GE:
-    return RISCVCC::COND_LT;
-  case RISCVCC::COND_LTU:
-    return RISCVCC::COND_GEU;
-  case RISCVCC::COND_GEU:
-    return RISCVCC::COND_LTU;
-  }
-}
-
 bool RISCVInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
                                    MachineBasicBlock *&TBB,
                                    MachineBasicBlock *&FBB,

llvm/lib/Target/RISCV/RISCVInstrInfo.h

@@ -44,7 +44,12 @@ enum CondCode {
   COND_INVALID
 };
 
-CondCode getOppositeBranchCondition(CondCode);
+CondCode getOppositeBranchCondition(CondCode CC) {
+  // To reverse a condition it's necessary to only invert the low bit:
+  assert(CC != COND_INVALID && "COND_INVALID has no inverse!");
+  return static_cast<CondCode>(static_cast<unsigned>(CC) ^ 0x1);
+}
+
 unsigned getBrCond(CondCode CC, unsigned SelectOpc = 0);
 
 } // end of namespace RISCVCC

llvm/lib/Target/XCore/XCoreInstrInfo.cpp

@@ -150,13 +150,11 @@ static inline unsigned GetCondBranchFromCond(XCore::CondCode CC)
 
 /// GetOppositeBranchCondition - Return the inverse of the specified
 /// condition, e.g. turning COND_E to COND_NE.
-static inline XCore::CondCode GetOppositeBranchCondition(XCore::CondCode CC)
-{
-  switch (CC) {
-  default: llvm_unreachable("Illegal condition code!");
-  case XCore::COND_TRUE   : return XCore::COND_FALSE;
-  case XCore::COND_FALSE  : return XCore::COND_TRUE;
-  }
+static inline XCore::CondCode GetOppositeBranchCondition(XCore::CondCode CC) {
+  // To reverse a condition it's necessary to only invert the low bit:
+  assert(CC != XCore::COND_INVALID && "COND_INVALID has no inverse!");
+
+  return static_cast<CondCode>(static_cast<unsigned>(CC) ^ 0x1);
 }
 
 /// analyzeBranch - Analyze the branching code at the end of MBB, returning