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[RISCV] Use SelectAddrRegRegScale for Xqcisls instructions. (#145608)
This reuses code from XTHeadMemIdex. This saves ~500 bytes from the isel table and provides more flexibility in what patterns can be matched.
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-40
lines changed

4 files changed

+36
-40
lines changed

‎llvm/lib/Target/RISCV/RISCVInstrInfo.td‎

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -502,6 +502,12 @@ def uimm6gt32 : ImmLeaf<XLenVT, [{
502502
// Addressing modes.
503503
def AddrRegImm : ComplexPattern<iPTR, 2, "SelectAddrRegImm">;
504504

505+
class AddrRegRegScale<int N>
506+
: ComplexPattern<iPTR, 3, "SelectAddrRegRegScale<"#N#">">;
507+
class AddrRegZextRegScale<int N>
508+
: ComplexPattern<i64, 3, "SelectAddrRegZextRegScale<"#N#", 32>",
509+
[], [], 10>;
510+
505511
// Return the negation of an immediate value.
506512
def NegImm : SDNodeXForm<imm, [{
507513
return CurDAG->getSignedTargetConstant(-N->getSExtValue(), SDLoc(N),

‎llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td‎

Lines changed: 6 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -743,32 +743,30 @@ def TH_SYNC_I : THCacheInst_void<0b11010, "th.sync.i">;
743743
def TH_SYNC_IS : THCacheInst_void<0b11011, "th.sync.is">;
744744
}
745745

746-
def AddrRegRegScale : ComplexPattern<iPTR, 3, "SelectAddrRegRegScale<3>">;
747-
def AddrRegZextRegScale
748-
: ComplexPattern<i64, 3, "SelectAddrRegZextRegScale<3, 32>",
749-
[], [], 10>;
746+
def AddrRegRegScale3 : AddrRegRegScale<3>;
747+
def AddrRegZextRegScale3 : AddrRegZextRegScale<3>;
750748

751749
multiclass LdIdxPat<PatFrag LoadOp, RVInst Inst, ValueType vt = XLenVT> {
752-
def : Pat<(vt (LoadOp (AddrRegRegScale (XLenVT GPR:$rs1), (XLenVT GPR:$rs2), uimm2:$uimm2))),
750+
def : Pat<(vt (LoadOp (AddrRegRegScale3 (XLenVT GPR:$rs1), (XLenVT GPR:$rs2), uimm2:$uimm2))),
753751
(Inst GPR:$rs1, GPR:$rs2, uimm2:$uimm2)>;
754752
}
755753

756754
multiclass LdZextIdxPat<PatFrag LoadOp, RVInst Inst, ValueType vt = i64> {
757-
def : Pat<(vt (LoadOp (AddrRegZextRegScale (i64 GPR:$rs1), (i64 GPR:$rs2), uimm2:$uimm2))),
755+
def : Pat<(vt (LoadOp (AddrRegZextRegScale3 (i64 GPR:$rs1), (i64 GPR:$rs2), uimm2:$uimm2))),
758756
(Inst GPR:$rs1, GPR:$rs2, uimm2:$uimm2)>;
759757
}
760758

761759
multiclass StIdxPat<PatFrag StoreOp, RVInst Inst, RegisterClass StTy,
762760
ValueType vt = XLenVT> {
763761
def : Pat<(StoreOp (vt StTy:$rd),
764-
(AddrRegRegScale (XLenVT GPR:$rs1), (XLenVT GPR:$rs2), uimm2:$uimm2)),
762+
(AddrRegRegScale3 (XLenVT GPR:$rs1), (XLenVT GPR:$rs2), uimm2:$uimm2)),
765763
(Inst StTy:$rd, GPR:$rs1, GPR:$rs2, uimm2:$uimm2)>;
766764
}
767765

768766
multiclass StZextIdxPat<PatFrag StoreOp, RVInst Inst, RegisterClass StTy,
769767
ValueType vt = i64> {
770768
def : Pat<(StoreOp (vt StTy:$rd),
771-
(AddrRegZextRegScale (i64 GPR:$rs1), (i64 GPR:$rs2), uimm2:$uimm2)),
769+
(AddrRegZextRegScale3 (i64 GPR:$rs1), (i64 GPR:$rs2), uimm2:$uimm2)),
772770
(Inst StTy:$rd, GPR:$rs1, GPR:$rs2, uimm2:$uimm2)>;
773771
}
774772

‎llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td‎

Lines changed: 4 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -198,9 +198,6 @@ def AddLike: PatFrags<(ops node:$A, node:$B),
198198
return CurDAG->isBaseWithConstantOffset(SDValue(N, 0));
199199
}]>;
200200

201-
def AddShl : PatFrag<(ops node:$Ra, node:$Rb, node:$SH3),
202-
(add node:$Ra, (shl node:$Rb, node:$SH3))>;
203-
204201
def IntCCtoQCRISCVCC : SDNodeXForm<riscv_selectcc, [{
205202
ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
206203
int64_t Imm = cast<ConstantSDNode>(N->getOperand(1))->getSExtValue();
@@ -1327,12 +1324,14 @@ class QC48StPat<PatFrag StoreOp, RVInst48 Inst>
13271324
: Pat<(StoreOp (i32 GPR:$rs2), (AddLike (i32 GPR:$rs1), simm26_nosimm12:$imm26)),
13281325
(Inst GPR:$rs2, GPR:$rs1, simm26_nosimm12:$imm26)>;
13291326

1327+
def AddrRegRegScale7 : AddrRegRegScale<7>;
1328+
13301329
class QCScaledLdPat<PatFrag LoadOp, RVInst Inst>
1331-
: Pat<(i32 (LoadOp (AddShl (i32 GPRMem:$rs1), (i32 GPRNoX0:$rs2), uimm3:$shamt))),
1330+
: Pat<(i32 (LoadOp (AddrRegRegScale7 (i32 GPRMem:$rs1), (i32 GPRNoX0:$rs2), uimm3:$shamt))),
13321331
(Inst GPRMem:$rs1, GPRNoX0:$rs2, uimm3:$shamt)>;
13331332

13341333
class QCScaledStPat<PatFrag StoreOp, RVInst Inst>
1335-
: Pat<(StoreOp (i32 GPR:$rd), (AddShl (i32 GPRMem:$rs1), (i32 GPRNoX0:$rs2), uimm3:$shamt)),
1334+
: Pat<(StoreOp (i32 GPR:$rd), (AddrRegRegScale7 (i32 GPRMem:$rs1), (i32 GPRNoX0:$rs2), uimm3:$shamt)),
13361335
(Inst GPR:$rd, GPRMem:$rs1, GPRNoX0:$rs2, uimm3:$shamt)>;
13371336

13381337
// Match `riscv_brcc` and lower to the appropriate XQCIBI branch instruction.

‎llvm/test/CodeGen/RISCV/xqcisls.ll‎

Lines changed: 20 additions & 27 deletions
Original file line numberDiff line numberDiff line change
@@ -221,8 +221,7 @@ define i8 @lrb_anyext(ptr %a, i64 %b) {
221221
;
222222
; RV32IZBAXQCISLS-LABEL: lrb_anyext:
223223
; RV32IZBAXQCISLS: # %bb.0:
224-
; RV32IZBAXQCISLS-NEXT: add a0, a0, a1
225-
; RV32IZBAXQCISLS-NEXT: lbu a0, 0(a0)
224+
; RV32IZBAXQCISLS-NEXT: qc.lrbu a0, a0, a1, 0
226225
; RV32IZBAXQCISLS-NEXT: ret
227226
%1 = getelementptr i8, ptr %a, i64 %b
228227
%2 = load i8, ptr %1, align 1
@@ -254,8 +253,7 @@ define i64 @lrb(ptr %a, i64 %b) {
254253
;
255254
; RV32IZBAXQCISLS-LABEL: lrb:
256255
; RV32IZBAXQCISLS: # %bb.0:
257-
; RV32IZBAXQCISLS-NEXT: add a0, a0, a1
258-
; RV32IZBAXQCISLS-NEXT: lb a1, 0(a0)
256+
; RV32IZBAXQCISLS-NEXT: qc.lrb a1, a0, a1, 0
259257
; RV32IZBAXQCISLS-NEXT: srai a2, a1, 31
260258
; RV32IZBAXQCISLS-NEXT: add a0, a1, a1
261259
; RV32IZBAXQCISLS-NEXT: sltu a1, a0, a1
@@ -284,8 +282,7 @@ define i8 @lurb_anyext(ptr %a, i32 %b) {
284282
;
285283
; RV32IZBAXQCISLS-LABEL: lurb_anyext:
286284
; RV32IZBAXQCISLS: # %bb.0:
287-
; RV32IZBAXQCISLS-NEXT: add a0, a0, a1
288-
; RV32IZBAXQCISLS-NEXT: lbu a0, 0(a0)
285+
; RV32IZBAXQCISLS-NEXT: qc.lrbu a0, a0, a1, 0
289286
; RV32IZBAXQCISLS-NEXT: ret
290287
%1 = zext i32 %b to i64
291288
%2 = getelementptr i8, ptr %a, i64 %1
@@ -318,8 +315,7 @@ define i64 @lurb(ptr %a, i32 %b) {
318315
;
319316
; RV32IZBAXQCISLS-LABEL: lurb:
320317
; RV32IZBAXQCISLS: # %bb.0:
321-
; RV32IZBAXQCISLS-NEXT: add a0, a0, a1
322-
; RV32IZBAXQCISLS-NEXT: lb a1, 0(a0)
318+
; RV32IZBAXQCISLS-NEXT: qc.lrb a1, a0, a1, 0
323319
; RV32IZBAXQCISLS-NEXT: srai a2, a1, 31
324320
; RV32IZBAXQCISLS-NEXT: add a0, a1, a1
325321
; RV32IZBAXQCISLS-NEXT: sltu a1, a0, a1
@@ -353,8 +349,7 @@ define i64 @lrbu(ptr %a, i64 %b) {
353349
;
354350
; RV32IZBAXQCISLS-LABEL: lrbu:
355351
; RV32IZBAXQCISLS: # %bb.0:
356-
; RV32IZBAXQCISLS-NEXT: add a0, a0, a1
357-
; RV32IZBAXQCISLS-NEXT: lbu a1, 0(a0)
352+
; RV32IZBAXQCISLS-NEXT: qc.lrbu a1, a0, a1, 0
358353
; RV32IZBAXQCISLS-NEXT: add a0, a1, a1
359354
; RV32IZBAXQCISLS-NEXT: sltu a1, a0, a1
360355
; RV32IZBAXQCISLS-NEXT: ret
@@ -384,8 +379,7 @@ define i64 @lurbu(ptr %a, i32 %b) {
384379
;
385380
; RV32IZBAXQCISLS-LABEL: lurbu:
386381
; RV32IZBAXQCISLS: # %bb.0:
387-
; RV32IZBAXQCISLS-NEXT: add a0, a0, a1
388-
; RV32IZBAXQCISLS-NEXT: lbu a1, 0(a0)
382+
; RV32IZBAXQCISLS-NEXT: qc.lrbu a1, a0, a1, 0
389383
; RV32IZBAXQCISLS-NEXT: add a0, a1, a1
390384
; RV32IZBAXQCISLS-NEXT: sltu a1, a0, a1
391385
; RV32IZBAXQCISLS-NEXT: ret
@@ -423,13 +417,14 @@ define i64 @lrd_2(ptr %a, i64 %b) {
423417
;
424418
; RV32IZBAXQCISLS-LABEL: lrd_2:
425419
; RV32IZBAXQCISLS: # %bb.0:
426-
; RV32IZBAXQCISLS-NEXT: sh3add a0, a1, a0
427-
; RV32IZBAXQCISLS-NEXT: lw a1, 96(a0)
428-
; RV32IZBAXQCISLS-NEXT: lw a2, 100(a0)
429-
; RV32IZBAXQCISLS-NEXT: add a0, a1, a1
430-
; RV32IZBAXQCISLS-NEXT: sltu a1, a0, a1
431-
; RV32IZBAXQCISLS-NEXT: add a2, a2, a2
432-
; RV32IZBAXQCISLS-NEXT: add a1, a2, a1
420+
; RV32IZBAXQCISLS-NEXT: addi a2, a0, 96
421+
; RV32IZBAXQCISLS-NEXT: qc.lrw a2, a2, a1, 3
422+
; RV32IZBAXQCISLS-NEXT: addi a0, a0, 100
423+
; RV32IZBAXQCISLS-NEXT: qc.lrw a1, a0, a1, 3
424+
; RV32IZBAXQCISLS-NEXT: add a0, a2, a2
425+
; RV32IZBAXQCISLS-NEXT: sltu a2, a0, a2
426+
; RV32IZBAXQCISLS-NEXT: add a1, a1, a1
427+
; RV32IZBAXQCISLS-NEXT: add a1, a1, a2
433428
; RV32IZBAXQCISLS-NEXT: ret
434429
%1 = add i64 %b, 12
435430
%2 = getelementptr i64, ptr %a, i64 %1
@@ -456,8 +451,7 @@ define void @srb(ptr %a, i64 %b, i8 %c) {
456451
; RV32IZBAXQCISLS-LABEL: srb:
457452
; RV32IZBAXQCISLS: # %bb.0:
458453
; RV32IZBAXQCISLS-NEXT: add a3, a3, a3
459-
; RV32IZBAXQCISLS-NEXT: add a0, a0, a1
460-
; RV32IZBAXQCISLS-NEXT: sb a3, 0(a0)
454+
; RV32IZBAXQCISLS-NEXT: qc.srb a3, a0, a1, 0
461455
; RV32IZBAXQCISLS-NEXT: ret
462456
%1 = add i8 %c, %c
463457
%2 = getelementptr i8, ptr %a, i64 %b
@@ -483,8 +477,7 @@ define void @surb(ptr %a, i32 %b, i8 %c) {
483477
; RV32IZBAXQCISLS-LABEL: surb:
484478
; RV32IZBAXQCISLS: # %bb.0:
485479
; RV32IZBAXQCISLS-NEXT: add a2, a2, a2
486-
; RV32IZBAXQCISLS-NEXT: add a0, a0, a1
487-
; RV32IZBAXQCISLS-NEXT: sb a2, 0(a0)
480+
; RV32IZBAXQCISLS-NEXT: qc.srb a2, a0, a1, 0
488481
; RV32IZBAXQCISLS-NEXT: ret
489482
%1 = zext i32 %b to i64
490483
%2 = add i8 %c, %c
@@ -512,10 +505,10 @@ define i64 @lrd_large_shift(ptr %a, i64 %b) {
512505
;
513506
; RV32IZBAXQCISLS-LABEL: lrd_large_shift:
514507
; RV32IZBAXQCISLS: # %bb.0:
515-
; RV32IZBAXQCISLS-NEXT: slli a1, a1, 5
516-
; RV32IZBAXQCISLS-NEXT: add a1, a1, a0
517-
; RV32IZBAXQCISLS-NEXT: lw a0, 384(a1)
518-
; RV32IZBAXQCISLS-NEXT: lw a1, 388(a1)
508+
; RV32IZBAXQCISLS-NEXT: addi a2, a0, 384
509+
; RV32IZBAXQCISLS-NEXT: addi a3, a0, 388
510+
; RV32IZBAXQCISLS-NEXT: qc.lrw a0, a2, a1, 5
511+
; RV32IZBAXQCISLS-NEXT: qc.lrw a1, a3, a1, 5
519512
; RV32IZBAXQCISLS-NEXT: ret
520513
%1 = add i64 %b, 12
521514
%2 = shl i64 %1, 2

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