CMPXCHG8B better TP

NexusXe · NexusXe · commit ceec220213d7 · 2025-10-01T14:16:00.000-05:00
diff --git a/llvm/lib/Target/X86/X86ScheduleZnver4.td b/llvm/lib/Target/X86/X86ScheduleZnver4.td
@@ -661,7 +661,7 @@ def : InstRW<[Zn4WriteCMPXCHG8rm_LCMPXCHG8], (instrs CMPXCHG8rm, LCMPXCHG8)>;
 
 def Zn4WriteCMPXCHG8B : SchedWriteRes<[Zn4ALU0123]> {
   let Latency = 3; // FIXME: not from llvm-exegesis
-  let ReleaseAtCycles = [24];
+  let ReleaseAtCycles = [20];
   let NumMicroOps = 15;
 }
 def : InstRW<[Zn4WriteCMPXCHG8B], (instrs CMPXCHG8B)>;

Original file line number	Diff line number	Diff line change
`@@ -661,7 +661,7 @@ def : InstRW<[Zn4WriteCMPXCHG8rm_LCMPXCHG8], (instrs CMPXCHG8rm, LCMPXCHG8)>;`
`661`	`661`
`662`	`662`	`def Zn4WriteCMPXCHG8B : SchedWriteRes<[Zn4ALU0123]> {`
`663`	`663`	`let Latency = 3; // FIXME: not from llvm-exegesis`
`664`		`- let ReleaseAtCycles = [24];`
	`664`	`+ let ReleaseAtCycles = [20];`
`665`	`665`	`let NumMicroOps = 15;`
`666`	`666`	`}`
`667`	`667`	`def : InstRW<[Zn4WriteCMPXCHG8B], (instrs CMPXCHG8B)>;`