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[VPlan] Handle canonical VPWidenIntOrFpInduction in branch-condition simplification (#153539)
SimplifyBranchConditionForVFAndUF only recognized canonical IVs and a few PHI recipes in the loop header. With more IV-step optimizations, the canonical widen-canonical-iv can be replaced by a canonical VPWidenIntOrFpInduction, which the pass did not handle, causing regressions (missed simplifications). This patch replaces canonical VPWidenIntOrFpInduction with a StepVector in the vector preheader since the vector loop region only executes once.
1 parent 9aae8ef commit cf0e861

10 files changed

+218
-527
lines changed

‎llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp‎

Lines changed: 17 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1492,11 +1492,25 @@ static bool simplifyBranchConditionForVFAndUF(VPlan &Plan, ElementCount BestVF,
14921492
// The vector loop region only executes once. If possible, completely remove
14931493
// the region, otherwise replace the terminator controlling the latch with
14941494
// (BranchOnCond true).
1495+
// TODO: VPWidenIntOrFpInductionRecipe is only partially supported; add
1496+
// support for other non-canonical widen induction recipes (e.g.,
1497+
// VPWidenPointerInductionRecipe).
14951498
auto *Header = cast<VPBasicBlock>(VectorRegion->getEntry());
1496-
if (all_of(Header->phis(),
1497-
IsaPred<VPCanonicalIVPHIRecipe, VPEVLBasedIVPHIRecipe,
1498-
VPFirstOrderRecurrencePHIRecipe, VPPhi>)) {
1499+
if (all_of(Header->phis(), [](VPRecipeBase &Phi) {
1500+
if (auto *R = dyn_cast<VPWidenIntOrFpInductionRecipe>(&Phi))
1501+
return R->isCanonical();
1502+
return isa<VPCanonicalIVPHIRecipe, VPEVLBasedIVPHIRecipe,
1503+
VPFirstOrderRecurrencePHIRecipe, VPPhi>(&Phi);
1504+
})) {
14991505
for (VPRecipeBase &HeaderR : make_early_inc_range(Header->phis())) {
1506+
if (auto *R = dyn_cast<VPWidenIntOrFpInductionRecipe>(&HeaderR)) {
1507+
VPBuilder Builder(Plan.getVectorPreheader());
1508+
VPValue *StepV = Builder.createNaryOp(VPInstruction::StepVector, {},
1509+
R->getScalarType());
1510+
HeaderR.getVPSingleValue()->replaceAllUsesWith(StepV);
1511+
HeaderR.eraseFromParent();
1512+
continue;
1513+
}
15001514
auto *Phi = cast<VPPhiAccessors>(&HeaderR);
15011515
HeaderR.getVPSingleValue()->replaceAllUsesWith(Phi->getIncomingValue(0));
15021516
HeaderR.eraseFromParent();

‎llvm/test/Transforms/LoopVectorize/AArch64/conditional-branches-cost.ll‎

Lines changed: 65 additions & 185 deletions
Large diffs are not rendered by default.

‎llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-remove-loop-region.ll‎

Lines changed: 11 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -47,14 +47,9 @@ define void @load_store_interleave_group_tc_2(ptr noalias %data) {
4747
; VF4: [[VECTOR_PH]]:
4848
; VF4-NEXT: br label %[[VECTOR_BODY:.*]]
4949
; VF4: [[VECTOR_BODY]]:
50-
; VF4-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[PRED_STORE_CONTINUE6:.*]] ]
51-
; VF4-NEXT: [[VEC_IND:%.*]] = phi <4 x i8> [ <i8 0, i8 1, i8 2, i8 3>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[PRED_STORE_CONTINUE6]] ]
52-
; VF4-NEXT: [[TMP0:%.*]] = icmp ule <4 x i8> [[VEC_IND]], splat (i8 1)
53-
; VF4-NEXT: [[TMP1:%.*]] = extractelement <4 x i1> [[TMP0]], i32 0
54-
; VF4-NEXT: br i1 [[TMP1]], label %[[PRED_STORE_IF:.*]], label %[[PRED_STORE_CONTINUE:.*]]
50+
; VF4-NEXT: br i1 true, label %[[PRED_STORE_IF:.*]], label %[[PRED_STORE_CONTINUE:.*]]
5551
; VF4: [[PRED_STORE_IF]]:
56-
; VF4-NEXT: [[TMP2:%.*]] = add i64 [[INDEX]], 0
57-
; VF4-NEXT: [[TMP3:%.*]] = shl nsw i64 [[TMP2]], 1
52+
; VF4-NEXT: [[TMP3:%.*]] = shl nsw i64 0, 1
5853
; VF4-NEXT: [[TMP4:%.*]] = getelementptr inbounds i64, ptr [[DATA]], i64 [[TMP3]]
5954
; VF4-NEXT: [[TMP5:%.*]] = load i64, ptr [[TMP4]], align 8
6055
; VF4-NEXT: store i64 [[TMP5]], ptr [[TMP4]], align 8
@@ -64,11 +59,9 @@ define void @load_store_interleave_group_tc_2(ptr noalias %data) {
6459
; VF4-NEXT: store i64 [[TMP8]], ptr [[TMP7]], align 8
6560
; VF4-NEXT: br label %[[PRED_STORE_CONTINUE]]
6661
; VF4: [[PRED_STORE_CONTINUE]]:
67-
; VF4-NEXT: [[TMP9:%.*]] = extractelement <4 x i1> [[TMP0]], i32 1
68-
; VF4-NEXT: br i1 [[TMP9]], label %[[PRED_STORE_IF1:.*]], label %[[PRED_STORE_CONTINUE2:.*]]
62+
; VF4-NEXT: br i1 true, label %[[PRED_STORE_IF1:.*]], label %[[PRED_STORE_CONTINUE2:.*]]
6963
; VF4: [[PRED_STORE_IF1]]:
70-
; VF4-NEXT: [[TMP10:%.*]] = add i64 [[INDEX]], 1
71-
; VF4-NEXT: [[TMP11:%.*]] = shl nsw i64 [[TMP10]], 1
64+
; VF4-NEXT: [[TMP11:%.*]] = shl nsw i64 1, 1
7265
; VF4-NEXT: [[TMP12:%.*]] = getelementptr inbounds i64, ptr [[DATA]], i64 [[TMP11]]
7366
; VF4-NEXT: [[TMP13:%.*]] = load i64, ptr [[TMP12]], align 8
7467
; VF4-NEXT: store i64 [[TMP13]], ptr [[TMP12]], align 8
@@ -78,11 +71,9 @@ define void @load_store_interleave_group_tc_2(ptr noalias %data) {
7871
; VF4-NEXT: store i64 [[TMP16]], ptr [[TMP15]], align 8
7972
; VF4-NEXT: br label %[[PRED_STORE_CONTINUE2]]
8073
; VF4: [[PRED_STORE_CONTINUE2]]:
81-
; VF4-NEXT: [[TMP17:%.*]] = extractelement <4 x i1> [[TMP0]], i32 2
82-
; VF4-NEXT: br i1 [[TMP17]], label %[[PRED_STORE_IF3:.*]], label %[[PRED_STORE_CONTINUE4:.*]]
74+
; VF4-NEXT: br i1 false, label %[[PRED_STORE_IF3:.*]], label %[[PRED_STORE_CONTINUE4:.*]]
8375
; VF4: [[PRED_STORE_IF3]]:
84-
; VF4-NEXT: [[TMP18:%.*]] = add i64 [[INDEX]], 2
85-
; VF4-NEXT: [[TMP19:%.*]] = shl nsw i64 [[TMP18]], 1
76+
; VF4-NEXT: [[TMP19:%.*]] = shl nsw i64 2, 1
8677
; VF4-NEXT: [[TMP20:%.*]] = getelementptr inbounds i64, ptr [[DATA]], i64 [[TMP19]]
8778
; VF4-NEXT: [[TMP21:%.*]] = load i64, ptr [[TMP20]], align 8
8879
; VF4-NEXT: store i64 [[TMP21]], ptr [[TMP20]], align 8
@@ -92,11 +83,9 @@ define void @load_store_interleave_group_tc_2(ptr noalias %data) {
9283
; VF4-NEXT: store i64 [[TMP24]], ptr [[TMP23]], align 8
9384
; VF4-NEXT: br label %[[PRED_STORE_CONTINUE4]]
9485
; VF4: [[PRED_STORE_CONTINUE4]]:
95-
; VF4-NEXT: [[TMP25:%.*]] = extractelement <4 x i1> [[TMP0]], i32 3
96-
; VF4-NEXT: br i1 [[TMP25]], label %[[PRED_STORE_IF5:.*]], label %[[PRED_STORE_CONTINUE6]]
86+
; VF4-NEXT: br i1 false, label %[[PRED_STORE_IF5:.*]], label %[[PRED_STORE_CONTINUE6:.*]]
9787
; VF4: [[PRED_STORE_IF5]]:
98-
; VF4-NEXT: [[TMP26:%.*]] = add i64 [[INDEX]], 3
99-
; VF4-NEXT: [[TMP27:%.*]] = shl nsw i64 [[TMP26]], 1
88+
; VF4-NEXT: [[TMP27:%.*]] = shl nsw i64 3, 1
10089
; VF4-NEXT: [[TMP28:%.*]] = getelementptr inbounds i64, ptr [[DATA]], i64 [[TMP27]]
10190
; VF4-NEXT: [[TMP29:%.*]] = load i64, ptr [[TMP28]], align 8
10291
; VF4-NEXT: store i64 [[TMP29]], ptr [[TMP28]], align 8
@@ -106,9 +95,7 @@ define void @load_store_interleave_group_tc_2(ptr noalias %data) {
10695
; VF4-NEXT: store i64 [[TMP32]], ptr [[TMP31]], align 8
10796
; VF4-NEXT: br label %[[PRED_STORE_CONTINUE6]]
10897
; VF4: [[PRED_STORE_CONTINUE6]]:
109-
; VF4-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
110-
; VF4-NEXT: [[VEC_IND_NEXT]] = add <4 x i8> [[VEC_IND]], splat (i8 4)
111-
; VF4-NEXT: br i1 true, label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
98+
; VF4-NEXT: br label %[[MIDDLE_BLOCK:.*]]
11299
; VF4: [[MIDDLE_BLOCK]]:
113100
; VF4-NEXT: br label %[[EXIT:.*]]
114101
; VF4: [[SCALAR_PH]]:
@@ -125,7 +112,7 @@ define void @load_store_interleave_group_tc_2(ptr noalias %data) {
125112
; VF4-NEXT: store i64 [[L_1]], ptr [[DATA_1]], align 8
126113
; VF4-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
127114
; VF4-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], 2
128-
; VF4-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP3:![0-9]+]]
115+
; VF4-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP0:![0-9]+]]
129116
; VF4: [[EXIT]]:
130117
; VF4-NEXT: ret void
131118
;
@@ -315,7 +302,7 @@ define void @test_complex_add_float_tc_4(ptr %res, ptr noalias %A, ptr noalias %
315302
; VF4-NEXT: store float [[ADD_1]], ptr [[GEP_RES_1]], align 4
316303
; VF4-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
317304
; VF4-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], 4
318-
; VF4-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP4:![0-9]+]]
305+
; VF4-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP3:![0-9]+]]
319306
; VF4: [[EXIT]]:
320307
; VF4-NEXT: ret void
321308
;

‎llvm/test/Transforms/LoopVectorize/X86/constant-fold.ll‎

Lines changed: 16 additions & 34 deletions
Original file line numberDiff line numberDiff line change
@@ -70,46 +70,37 @@ define void @redundant_or_1(ptr %dst, i1 %c.0, i1 %c.1) {
7070
; CHECK-NEXT: [[BROADCAST_SPLAT2:%.*]] = shufflevector <4 x i1> [[BROADCAST_SPLATINSERT1]], <4 x i1> poison, <4 x i32> zeroinitializer
7171
; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
7272
; CHECK: vector.body:
73-
; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[PRED_STORE_CONTINUE8:%.*]] ]
74-
; CHECK-NEXT: [[VEC_IND:%.*]] = phi <4 x i8> [ <i8 0, i8 1, i8 2, i8 3>, [[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], [[PRED_STORE_CONTINUE8]] ]
75-
; CHECK-NEXT: [[TMP1:%.*]] = icmp ule <4 x i8> [[VEC_IND]], splat (i8 2)
76-
; CHECK-NEXT: [[TMP2:%.*]] = select <4 x i1> [[TMP1]], <4 x i1> [[TMP0]], <4 x i1> zeroinitializer
73+
; CHECK-NEXT: [[TMP2:%.*]] = select <4 x i1> <i1 true, i1 true, i1 true, i1 false>, <4 x i1> [[TMP0]], <4 x i1> zeroinitializer
7774
; CHECK-NEXT: [[TMP5:%.*]] = select <4 x i1> [[TMP2]], <4 x i1> [[BROADCAST_SPLAT2]], <4 x i1> zeroinitializer
7875
; CHECK-NEXT: [[TMP6:%.*]] = extractelement <4 x i1> [[TMP5]], i32 0
7976
; CHECK-NEXT: br i1 [[TMP6]], label [[PRED_STORE_IF:%.*]], label [[PRED_STORE_CONTINUE:%.*]]
8077
; CHECK: pred.store.if:
81-
; CHECK-NEXT: [[TMP7:%.*]] = add i32 [[INDEX]], 0
82-
; CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds i32, ptr [[DST:%.*]], i32 [[TMP7]]
78+
; CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds i32, ptr [[DST:%.*]], i32 0
8379
; CHECK-NEXT: store i32 0, ptr [[TMP8]], align 4
8480
; CHECK-NEXT: br label [[PRED_STORE_CONTINUE]]
8581
; CHECK: pred.store.continue:
8682
; CHECK-NEXT: [[TMP9:%.*]] = extractelement <4 x i1> [[TMP5]], i32 1
8783
; CHECK-NEXT: br i1 [[TMP9]], label [[PRED_STORE_IF3:%.*]], label [[PRED_STORE_CONTINUE4:%.*]]
8884
; CHECK: pred.store.if3:
89-
; CHECK-NEXT: [[TMP10:%.*]] = add i32 [[INDEX]], 1
90-
; CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds i32, ptr [[DST]], i32 [[TMP10]]
85+
; CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds i32, ptr [[DST]], i32 1
9186
; CHECK-NEXT: store i32 0, ptr [[TMP11]], align 4
9287
; CHECK-NEXT: br label [[PRED_STORE_CONTINUE4]]
9388
; CHECK: pred.store.continue4:
9489
; CHECK-NEXT: [[TMP12:%.*]] = extractelement <4 x i1> [[TMP5]], i32 2
9590
; CHECK-NEXT: br i1 [[TMP12]], label [[PRED_STORE_IF5:%.*]], label [[PRED_STORE_CONTINUE6:%.*]]
9691
; CHECK: pred.store.if5:
97-
; CHECK-NEXT: [[TMP13:%.*]] = add i32 [[INDEX]], 2
98-
; CHECK-NEXT: [[TMP14:%.*]] = getelementptr inbounds i32, ptr [[DST]], i32 [[TMP13]]
92+
; CHECK-NEXT: [[TMP14:%.*]] = getelementptr inbounds i32, ptr [[DST]], i32 2
9993
; CHECK-NEXT: store i32 0, ptr [[TMP14]], align 4
10094
; CHECK-NEXT: br label [[PRED_STORE_CONTINUE6]]
10195
; CHECK: pred.store.continue6:
10296
; CHECK-NEXT: [[TMP15:%.*]] = extractelement <4 x i1> [[TMP5]], i32 3
103-
; CHECK-NEXT: br i1 [[TMP15]], label [[PRED_STORE_IF7:%.*]], label [[PRED_STORE_CONTINUE8]]
97+
; CHECK-NEXT: br i1 [[TMP15]], label [[PRED_STORE_IF7:%.*]], label [[PRED_STORE_CONTINUE8:%.*]]
10498
; CHECK: pred.store.if7:
105-
; CHECK-NEXT: [[TMP16:%.*]] = add i32 [[INDEX]], 3
106-
; CHECK-NEXT: [[TMP17:%.*]] = getelementptr inbounds i32, ptr [[DST]], i32 [[TMP16]]
99+
; CHECK-NEXT: [[TMP17:%.*]] = getelementptr inbounds i32, ptr [[DST]], i32 3
107100
; CHECK-NEXT: store i32 0, ptr [[TMP17]], align 4
108101
; CHECK-NEXT: br label [[PRED_STORE_CONTINUE8]]
109102
; CHECK: pred.store.continue8:
110-
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4
111-
; CHECK-NEXT: [[VEC_IND_NEXT]] = add <4 x i8> [[VEC_IND]], splat (i8 4)
112-
; CHECK-NEXT: br i1 true, label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]]
103+
; CHECK-NEXT: br label [[MIDDLE_BLOCK:%.*]]
113104
; CHECK: middle.block:
114105
; CHECK-NEXT: br label [[EXIT:%.*]]
115106
; CHECK: scalar.ph:
@@ -129,7 +120,7 @@ define void @redundant_or_1(ptr %dst, i1 %c.0, i1 %c.1) {
129120
; CHECK: loop.latch:
130121
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 1
131122
; CHECK-NEXT: [[EC:%.*]] = icmp eq i32 [[IV_NEXT]], 3
132-
; CHECK-NEXT: br i1 [[EC]], label [[EXIT]], label [[LOOP_HEADER]], !llvm.loop [[LOOP4:![0-9]+]]
123+
; CHECK-NEXT: br i1 [[EC]], label [[EXIT]], label [[LOOP_HEADER]], !llvm.loop [[LOOP3:![0-9]+]]
133124
; CHECK: exit:
134125
; CHECK-NEXT: ret void
135126
;
@@ -172,46 +163,37 @@ define void @redundant_or_2(ptr %dst, i1 %c.0, i1 %c.1) {
172163
; CHECK-NEXT: [[BROADCAST_SPLAT2:%.*]] = shufflevector <4 x i1> [[BROADCAST_SPLATINSERT1]], <4 x i1> poison, <4 x i32> zeroinitializer
173164
; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
174165
; CHECK: vector.body:
175-
; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[PRED_STORE_CONTINUE8:%.*]] ]
176-
; CHECK-NEXT: [[VEC_IND:%.*]] = phi <4 x i8> [ <i8 0, i8 1, i8 2, i8 3>, [[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], [[PRED_STORE_CONTINUE8]] ]
177-
; CHECK-NEXT: [[TMP2:%.*]] = icmp ule <4 x i8> [[VEC_IND]], splat (i8 2)
178-
; CHECK-NEXT: [[TMP3:%.*]] = select <4 x i1> [[TMP2]], <4 x i1> [[TMP0]], <4 x i1> zeroinitializer
166+
; CHECK-NEXT: [[TMP3:%.*]] = select <4 x i1> <i1 true, i1 true, i1 true, i1 false>, <4 x i1> [[TMP0]], <4 x i1> zeroinitializer
179167
; CHECK-NEXT: [[TMP4:%.*]] = select <4 x i1> [[TMP3]], <4 x i1> [[BROADCAST_SPLAT2]], <4 x i1> zeroinitializer
180168
; CHECK-NEXT: [[TMP5:%.*]] = extractelement <4 x i1> [[TMP4]], i32 0
181169
; CHECK-NEXT: br i1 [[TMP5]], label [[PRED_STORE_IF:%.*]], label [[PRED_STORE_CONTINUE:%.*]]
182170
; CHECK: pred.store.if:
183-
; CHECK-NEXT: [[TMP6:%.*]] = add i32 [[INDEX]], 0
184-
; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds i32, ptr [[DST:%.*]], i32 [[TMP6]]
171+
; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds i32, ptr [[DST:%.*]], i32 0
185172
; CHECK-NEXT: store i32 0, ptr [[TMP7]], align 4
186173
; CHECK-NEXT: br label [[PRED_STORE_CONTINUE]]
187174
; CHECK: pred.store.continue:
188175
; CHECK-NEXT: [[TMP8:%.*]] = extractelement <4 x i1> [[TMP4]], i32 1
189176
; CHECK-NEXT: br i1 [[TMP8]], label [[PRED_STORE_IF3:%.*]], label [[PRED_STORE_CONTINUE4:%.*]]
190177
; CHECK: pred.store.if3:
191-
; CHECK-NEXT: [[TMP9:%.*]] = add i32 [[INDEX]], 1
192-
; CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds i32, ptr [[DST]], i32 [[TMP9]]
178+
; CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds i32, ptr [[DST]], i32 1
193179
; CHECK-NEXT: store i32 0, ptr [[TMP10]], align 4
194180
; CHECK-NEXT: br label [[PRED_STORE_CONTINUE4]]
195181
; CHECK: pred.store.continue4:
196182
; CHECK-NEXT: [[TMP11:%.*]] = extractelement <4 x i1> [[TMP4]], i32 2
197183
; CHECK-NEXT: br i1 [[TMP11]], label [[PRED_STORE_IF5:%.*]], label [[PRED_STORE_CONTINUE6:%.*]]
198184
; CHECK: pred.store.if5:
199-
; CHECK-NEXT: [[TMP12:%.*]] = add i32 [[INDEX]], 2
200-
; CHECK-NEXT: [[TMP13:%.*]] = getelementptr inbounds i32, ptr [[DST]], i32 [[TMP12]]
185+
; CHECK-NEXT: [[TMP13:%.*]] = getelementptr inbounds i32, ptr [[DST]], i32 2
201186
; CHECK-NEXT: store i32 0, ptr [[TMP13]], align 4
202187
; CHECK-NEXT: br label [[PRED_STORE_CONTINUE6]]
203188
; CHECK: pred.store.continue6:
204189
; CHECK-NEXT: [[TMP14:%.*]] = extractelement <4 x i1> [[TMP4]], i32 3
205-
; CHECK-NEXT: br i1 [[TMP14]], label [[PRED_STORE_IF7:%.*]], label [[PRED_STORE_CONTINUE8]]
190+
; CHECK-NEXT: br i1 [[TMP14]], label [[PRED_STORE_IF7:%.*]], label [[PRED_STORE_CONTINUE8:%.*]]
206191
; CHECK: pred.store.if7:
207-
; CHECK-NEXT: [[TMP15:%.*]] = add i32 [[INDEX]], 3
208-
; CHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds i32, ptr [[DST]], i32 [[TMP15]]
192+
; CHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds i32, ptr [[DST]], i32 3
209193
; CHECK-NEXT: store i32 0, ptr [[TMP16]], align 4
210194
; CHECK-NEXT: br label [[PRED_STORE_CONTINUE8]]
211195
; CHECK: pred.store.continue8:
212-
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4
213-
; CHECK-NEXT: [[VEC_IND_NEXT]] = add <4 x i8> [[VEC_IND]], splat (i8 4)
214-
; CHECK-NEXT: br i1 true, label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP5:![0-9]+]]
196+
; CHECK-NEXT: br label [[MIDDLE_BLOCK:%.*]]
215197
; CHECK: middle.block:
216198
; CHECK-NEXT: br label [[EXIT:%.*]]
217199
; CHECK: scalar.ph:
@@ -231,7 +213,7 @@ define void @redundant_or_2(ptr %dst, i1 %c.0, i1 %c.1) {
231213
; CHECK: loop.latch:
232214
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 1
233215
; CHECK-NEXT: [[EC:%.*]] = icmp eq i32 [[IV_NEXT]], 3
234-
; CHECK-NEXT: br i1 [[EC]], label [[EXIT]], label [[LOOP_HEADER]], !llvm.loop [[LOOP6:![0-9]+]]
216+
; CHECK-NEXT: br i1 [[EC]], label [[EXIT]], label [[LOOP_HEADER]], !llvm.loop [[LOOP4:![0-9]+]]
235217
; CHECK: exit:
236218
; CHECK-NEXT: ret void
237219
;

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