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[GlobalISel] Add G_CONCAT_VECTOR handling in computeNumSignBits (#142355)
Code ported from SelectionDAG::ComputeNumSignBits
1 parent ac42923 commit cf348e8

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7 files changed

+50
-47
lines changed

7 files changed

+50
-47
lines changed

‎llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp‎

Lines changed: 25 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1958,6 +1958,31 @@ unsigned GISelValueTracking::computeNumSignBits(Register R,
19581958
}
19591959
break;
19601960
}
1961+
case TargetOpcode::G_CONCAT_VECTORS: {
1962+
if (MRI.getType(MI.getOperand(0).getReg()).isScalableVector())
1963+
break;
1964+
FirstAnswer = TyBits;
1965+
// Determine the minimum number of sign bits across all demanded
1966+
// elts of the input vectors. Early out if the result is already 1.
1967+
unsigned NumSubVectorElts =
1968+
MRI.getType(MI.getOperand(1).getReg()).getNumElements();
1969+
unsigned NumSubVectors = MI.getNumOperands() - 1;
1970+
for (unsigned i = 0; i < NumSubVectors; ++i) {
1971+
APInt DemandedSub =
1972+
DemandedElts.extractBits(NumSubVectorElts, i * NumSubVectorElts);
1973+
if (!DemandedSub)
1974+
continue;
1975+
unsigned Tmp2 = computeNumSignBits(MI.getOperand(i + 1).getReg(),
1976+
DemandedSub, Depth + 1);
1977+
1978+
FirstAnswer = std::min(FirstAnswer, Tmp2);
1979+
1980+
// If we don't know any bits, early out.
1981+
if (FirstAnswer == 1)
1982+
break;
1983+
}
1984+
break;
1985+
}
19611986
case TargetOpcode::G_SHUFFLE_VECTOR: {
19621987
// Collect the minimum number of sign bits that are shared by every vector
19631988
// element referenced by the shuffle.

‎llvm/test/CodeGen/AArch64/GlobalISel/knownbits-concat.mir‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -42,7 +42,7 @@ body: |
4242
; CHECK-NEXT: %1:_ KnownBits:???????? SignBits:1
4343
; CHECK-NEXT: %sext0:_ KnownBits:???????????????? SignBits:9
4444
; CHECK-NEXT: %sext1:_ KnownBits:???????????????? SignBits:9
45-
; CHECK-NEXT: %res:_ KnownBits:???????????????? SignBits:1
45+
; CHECK-NEXT: %res:_ KnownBits:???????????????? SignBits:9
4646
%0:_(<2 x s8>) = COPY $h0
4747
%1:_(<2 x s8>) = COPY $h1
4848
%sext0:_(<2 x s16>) = G_SEXT %0
@@ -60,7 +60,7 @@ body: |
6060
; CHECK-NEXT: %1:_ KnownBits:???????? SignBits:1
6161
; CHECK-NEXT: %zext0:_ KnownBits:00000000???????? SignBits:8
6262
; CHECK-NEXT: %sext1:_ KnownBits:???????????????? SignBits:9
63-
; CHECK-NEXT: %res:_ KnownBits:???????????????? SignBits:1
63+
; CHECK-NEXT: %res:_ KnownBits:???????????????? SignBits:8
6464
%0:_(<2 x s8>) = COPY $h0
6565
%1:_(<2 x s8>) = COPY $h1
6666
%zext0:_(<2 x s16>) = G_ZEXT %0

‎llvm/test/CodeGen/AArch64/GlobalISel/legalize-min-max.mir‎

Lines changed: 16 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -249,14 +249,12 @@ body: |
249249
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<2 x s64>) = G_IMPLICIT_DEF
250250
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(slt), [[DEF]](<2 x s64>), [[DEF]]
251251
; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(slt), [[DEF]](<2 x s64>), [[DEF]]
252-
; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(<2 x s64>) = G_SEXT_INREG [[ICMP]], 1
253-
; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(<2 x s64>) = G_SEXT_INREG [[ICMP1]], 1
254252
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
255253
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
256-
; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x s64>) = G_XOR [[SEXT_INREG]], [[BUILD_VECTOR]]
257-
; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(<2 x s64>) = G_XOR [[SEXT_INREG1]], [[BUILD_VECTOR]]
258-
; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[SEXT_INREG]]
259-
; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[SEXT_INREG1]]
254+
; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x s64>) = G_XOR [[ICMP]], [[BUILD_VECTOR]]
255+
; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(<2 x s64>) = G_XOR [[ICMP1]], [[BUILD_VECTOR]]
256+
; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[ICMP]]
257+
; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[ICMP1]]
260258
; CHECK-NEXT: [[AND2:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[XOR]]
261259
; CHECK-NEXT: [[AND3:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[XOR1]]
262260
; CHECK-NEXT: [[OR:%[0-9]+]]:_(<2 x s64>) = G_OR [[AND]], [[AND2]]
@@ -521,14 +519,12 @@ body: |
521519
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<2 x s64>) = G_IMPLICIT_DEF
522520
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(ult), [[DEF]](<2 x s64>), [[DEF]]
523521
; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(ult), [[DEF]](<2 x s64>), [[DEF]]
524-
; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(<2 x s64>) = G_SEXT_INREG [[ICMP]], 1
525-
; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(<2 x s64>) = G_SEXT_INREG [[ICMP1]], 1
526522
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
527523
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
528-
; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x s64>) = G_XOR [[SEXT_INREG]], [[BUILD_VECTOR]]
529-
; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(<2 x s64>) = G_XOR [[SEXT_INREG1]], [[BUILD_VECTOR]]
530-
; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[SEXT_INREG]]
531-
; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[SEXT_INREG1]]
524+
; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x s64>) = G_XOR [[ICMP]], [[BUILD_VECTOR]]
525+
; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(<2 x s64>) = G_XOR [[ICMP1]], [[BUILD_VECTOR]]
526+
; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[ICMP]]
527+
; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[ICMP1]]
532528
; CHECK-NEXT: [[AND2:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[XOR]]
533529
; CHECK-NEXT: [[AND3:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[XOR1]]
534530
; CHECK-NEXT: [[OR:%[0-9]+]]:_(<2 x s64>) = G_OR [[AND]], [[AND2]]
@@ -793,14 +789,12 @@ body: |
793789
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<2 x s64>) = G_IMPLICIT_DEF
794790
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(sgt), [[DEF]](<2 x s64>), [[DEF]]
795791
; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(sgt), [[DEF]](<2 x s64>), [[DEF]]
796-
; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(<2 x s64>) = G_SEXT_INREG [[ICMP]], 1
797-
; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(<2 x s64>) = G_SEXT_INREG [[ICMP1]], 1
798792
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
799793
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
800-
; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x s64>) = G_XOR [[SEXT_INREG]], [[BUILD_VECTOR]]
801-
; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(<2 x s64>) = G_XOR [[SEXT_INREG1]], [[BUILD_VECTOR]]
802-
; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[SEXT_INREG]]
803-
; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[SEXT_INREG1]]
794+
; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x s64>) = G_XOR [[ICMP]], [[BUILD_VECTOR]]
795+
; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(<2 x s64>) = G_XOR [[ICMP1]], [[BUILD_VECTOR]]
796+
; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[ICMP]]
797+
; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[ICMP1]]
804798
; CHECK-NEXT: [[AND2:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[XOR]]
805799
; CHECK-NEXT: [[AND3:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[XOR1]]
806800
; CHECK-NEXT: [[OR:%[0-9]+]]:_(<2 x s64>) = G_OR [[AND]], [[AND2]]
@@ -1065,14 +1059,12 @@ body: |
10651059
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<2 x s64>) = G_IMPLICIT_DEF
10661060
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(ugt), [[DEF]](<2 x s64>), [[DEF]]
10671061
; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(ugt), [[DEF]](<2 x s64>), [[DEF]]
1068-
; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(<2 x s64>) = G_SEXT_INREG [[ICMP]], 1
1069-
; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(<2 x s64>) = G_SEXT_INREG [[ICMP1]], 1
10701062
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
10711063
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
1072-
; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x s64>) = G_XOR [[SEXT_INREG]], [[BUILD_VECTOR]]
1073-
; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(<2 x s64>) = G_XOR [[SEXT_INREG1]], [[BUILD_VECTOR]]
1074-
; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[SEXT_INREG]]
1075-
; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[SEXT_INREG1]]
1064+
; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x s64>) = G_XOR [[ICMP]], [[BUILD_VECTOR]]
1065+
; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(<2 x s64>) = G_XOR [[ICMP1]], [[BUILD_VECTOR]]
1066+
; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[ICMP]]
1067+
; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[ICMP1]]
10761068
; CHECK-NEXT: [[AND2:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[XOR]]
10771069
; CHECK-NEXT: [[AND3:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[XOR1]]
10781070
; CHECK-NEXT: [[OR:%[0-9]+]]:_(<2 x s64>) = G_OR [[AND]], [[AND2]]

‎llvm/test/CodeGen/AArch64/aarch64-dup-ext.ll‎

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -335,8 +335,6 @@ define void @typei1_orig(i64 %a, ptr %p, ptr %q) {
335335
; CHECK-GI-NEXT: cmtst v0.8h, v0.8h, v0.8h
336336
; CHECK-GI-NEXT: mvn v1.16b, v1.16b
337337
; CHECK-GI-NEXT: uzp1 v0.16b, v0.16b, v1.16b
338-
; CHECK-GI-NEXT: shl v0.16b, v0.16b, #7
339-
; CHECK-GI-NEXT: sshr v0.16b, v0.16b, #7
340338
; CHECK-GI-NEXT: str q0, [x1]
341339
; CHECK-GI-NEXT: ret
342340
%tmp = xor <16 x i1> zeroinitializer, <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>

‎llvm/test/CodeGen/AArch64/fcmp.ll‎

Lines changed: 7 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -969,8 +969,6 @@ define <4 x i32> @v4f64_i32(<4 x double> %a, <4 x double> %b, <4 x i32> %d, <4 x
969969
; CHECK-GI-NEXT: fcmgt v0.2d, v2.2d, v0.2d
970970
; CHECK-GI-NEXT: fcmgt v1.2d, v3.2d, v1.2d
971971
; CHECK-GI-NEXT: uzp1 v0.4s, v0.4s, v1.4s
972-
; CHECK-GI-NEXT: shl v0.4s, v0.4s, #31
973-
; CHECK-GI-NEXT: sshr v0.4s, v0.4s, #31
974972
; CHECK-GI-NEXT: bsl v0.16b, v4.16b, v5.16b
975973
; CHECK-GI-NEXT: ret
976974
entry:
@@ -1291,8 +1289,6 @@ define <8 x half> @v8f16_half(<8 x half> %a, <8 x half> %b, <8 x half> %d, <8 x
12911289
; CHECK-GI-NOFP16-NEXT: fcmgt v4.4s, v5.4s, v4.4s
12921290
; CHECK-GI-NOFP16-NEXT: fcmgt v0.4s, v1.4s, v0.4s
12931291
; CHECK-GI-NOFP16-NEXT: uzp1 v0.8h, v4.8h, v0.8h
1294-
; CHECK-GI-NOFP16-NEXT: shl v0.8h, v0.8h, #15
1295-
; CHECK-GI-NOFP16-NEXT: sshr v0.8h, v0.8h, #15
12961292
; CHECK-GI-NOFP16-NEXT: bsl v0.16b, v2.16b, v3.16b
12971293
; CHECK-GI-NOFP16-NEXT: ret
12981294
;
@@ -1341,9 +1337,9 @@ define <16 x half> @v16f16_half(<16 x half> %a, <16 x half> %b, <16 x half> %d,
13411337
; CHECK-GI-NOFP16-NEXT: fcvtl v16.4s, v0.4h
13421338
; CHECK-GI-NOFP16-NEXT: fcvtl2 v0.4s, v0.8h
13431339
; CHECK-GI-NOFP16-NEXT: fcvtl v17.4s, v1.4h
1344-
; CHECK-GI-NOFP16-NEXT: fcvtl2 v1.4s, v1.8h
13451340
; CHECK-GI-NOFP16-NEXT: fcvtl v18.4s, v2.4h
13461341
; CHECK-GI-NOFP16-NEXT: fcvtl2 v2.4s, v2.8h
1342+
; CHECK-GI-NOFP16-NEXT: fcvtl2 v1.4s, v1.8h
13471343
; CHECK-GI-NOFP16-NEXT: fcvtl v19.4s, v3.4h
13481344
; CHECK-GI-NOFP16-NEXT: fcvtl2 v3.4s, v3.8h
13491345
; CHECK-GI-NOFP16-NEXT: fcmgt v16.4s, v18.4s, v16.4s
@@ -1352,12 +1348,12 @@ define <16 x half> @v16f16_half(<16 x half> %a, <16 x half> %b, <16 x half> %d,
13521348
; CHECK-GI-NOFP16-NEXT: fcmgt v1.4s, v3.4s, v1.4s
13531349
; CHECK-GI-NOFP16-NEXT: uzp1 v0.8h, v16.8h, v0.8h
13541350
; CHECK-GI-NOFP16-NEXT: uzp1 v1.8h, v2.8h, v1.8h
1355-
; CHECK-GI-NOFP16-NEXT: shl v0.8h, v0.8h, #15
1356-
; CHECK-GI-NOFP16-NEXT: shl v1.8h, v1.8h, #15
1357-
; CHECK-GI-NOFP16-NEXT: sshr v0.8h, v0.8h, #15
1358-
; CHECK-GI-NOFP16-NEXT: sshr v1.8h, v1.8h, #15
1359-
; CHECK-GI-NOFP16-NEXT: bsl v0.16b, v4.16b, v6.16b
1360-
; CHECK-GI-NOFP16-NEXT: bsl v1.16b, v5.16b, v7.16b
1351+
; CHECK-GI-NOFP16-NEXT: and v2.16b, v4.16b, v0.16b
1352+
; CHECK-GI-NOFP16-NEXT: bic v0.16b, v6.16b, v0.16b
1353+
; CHECK-GI-NOFP16-NEXT: and v3.16b, v5.16b, v1.16b
1354+
; CHECK-GI-NOFP16-NEXT: bic v1.16b, v7.16b, v1.16b
1355+
; CHECK-GI-NOFP16-NEXT: orr v0.16b, v2.16b, v0.16b
1356+
; CHECK-GI-NOFP16-NEXT: orr v1.16b, v3.16b, v1.16b
13611357
; CHECK-GI-NOFP16-NEXT: ret
13621358
;
13631359
; CHECK-GI-FP16-LABEL: v16f16_half:

‎llvm/test/CodeGen/AArch64/scmp.ll‎

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -310,10 +310,6 @@ define <16 x i8> @signOf_neon_scmp(<8 x i16> %s0_lo, <8 x i16> %s0_hi, <8 x i16>
310310
; CHECK-GI-NEXT: cmgt v1.8h, v3.8h, v1.8h
311311
; CHECK-GI-NEXT: uzp1 v0.16b, v0.16b, v1.16b
312312
; CHECK-GI-NEXT: uzp1 v1.16b, v4.16b, v5.16b
313-
; CHECK-GI-NEXT: shl v0.16b, v0.16b, #7
314-
; CHECK-GI-NEXT: shl v1.16b, v1.16b, #7
315-
; CHECK-GI-NEXT: sshr v0.16b, v0.16b, #7
316-
; CHECK-GI-NEXT: sshr v1.16b, v1.16b, #7
317313
; CHECK-GI-NEXT: sub v0.16b, v0.16b, v1.16b
318314
; CHECK-GI-NEXT: ret
319315
entry:

‎llvm/test/CodeGen/AArch64/ucmp.ll‎

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -348,10 +348,6 @@ define <16 x i8> @signOf_neon(<8 x i16> %s0_lo, <8 x i16> %s0_hi, <8 x i16> %s1_
348348
; CHECK-GI-NEXT: cmhi v1.8h, v3.8h, v1.8h
349349
; CHECK-GI-NEXT: uzp1 v0.16b, v0.16b, v1.16b
350350
; CHECK-GI-NEXT: uzp1 v1.16b, v4.16b, v5.16b
351-
; CHECK-GI-NEXT: shl v0.16b, v0.16b, #7
352-
; CHECK-GI-NEXT: shl v1.16b, v1.16b, #7
353-
; CHECK-GI-NEXT: sshr v0.16b, v0.16b, #7
354-
; CHECK-GI-NEXT: sshr v1.16b, v1.16b, #7
355351
; CHECK-GI-NEXT: sub v0.16b, v0.16b, v1.16b
356352
; CHECK-GI-NEXT: ret
357353
entry:

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